ISG3300EU
PIN FUNCTIONS
Pin No.
Pin Name
Description
Equivalent Circuit
Clock pin for the dual PLL. High impedance
CMOS input. Data for the various latches is
clocked in on the rising edge into a 20-bit
shift register.
11
CLK
Serial data pin for the dual PLL. High
impedance CMOS input. MSB entered first.
The last two bits are the control bits.
12
13
DATA
LDEN
Latch enable pin for the dual PLL. High
impedance CMOS input. When LE goes
HIGH, data stored in the shift registers is
loaded into one of the 4 latches determined
by the 2 control bits.
14
15
GND
Ground.
Non-inverting final IF output.
5.6 µH 15
IFOUT+
240
16
IFOUT–
Inverting final IF output.
5.6 µH 16
240
Note:
1. For programming information, refer to National LMX2336 data sheet (http://www.national.com)
FIGURE 1
36.125 MHZ
91-860 MHz
RX OUT
DUAL PLL
CABLE
IN/OUT
OPTIONAL
CLK DATA LDEN
TX IN
5-65 MHz
CEL [ CALIFORNIA EASTERN LABS ]
