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CA24WC128JA-1.8TE13 参数 Datasheet PDF下载

CA24WC128JA-1.8TE13图片预览
型号: CA24WC128JA-1.8TE13
PDF下载: 下载PDF文件 查看货源
内容描述: 128K位I2C串行E2PROM CMOS [128K-Bit I2C Serial CMOS E2PROM]
分类和应用: 可编程只读存储器
文件页数/大小: 8 页 / 46 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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CAT24WC128  
Preliminary  
I2C BUS PROTOCOL  
PIN DESCRIPTIONS  
The features of the I2C bus protocol are defined as  
follows:  
SCL: Serial Clock  
The serial clock input clocks all data transferred into or  
out of the device.  
(1) Data transfer may be initiated only when the bus  
is not busy.  
SDA: Serial Data/Address  
The bidirectional serial data/address pin is used to  
transfer all data into and out of the device. The SDA pin  
is an open drain output and can be wire-ORed with  
other open drain or open collector outputs.  
(2) During a data transfer, the data line must remain  
stablewhenevertheclocklineishigh.Anychanges  
in the data line while the clock line is high will be  
interpreted as a START or STOP condition.  
WP: Write Protect  
START Condition  
This input, when tied to GND, allows write operations to  
the entire memory. When this pin is tied to Vcc, the  
entire memory is write protected. When left floating,  
memory is unprotected.  
The START Condition precedes all commands to the  
device, and is defined as a HIGH to LOW transition of  
SDA when SCL is HIGH. The CAT24WC128 monitors  
the SDA and SCL lines and will not respond until this  
condition is met.  
STOP Condition  
A LOW to HIGH transition of SDA when SCL is HIGH  
determines the STOP condition. All operations must  
end with a STOP condition.  
Figure 1. Bus Timing  
t
t
t
F
HIGH  
R
t
t
LOW  
LOW  
SCL  
t
t
HD:DAT  
SU:STA  
t
t
t
t
HD:STA  
SU:DAT  
SU:STO  
SDA IN  
BUF  
t
t
DH  
AA  
SDA OUT  
5020 FHD F03  
Figure 2. Write Cycle Timing  
SCL  
SDA  
8TH BIT  
BYTE n  
ACK  
t
WR  
STOP  
CONDITION  
START  
CONDITION  
ADDRESS  
5020 FHD F04  
Figure 3. Start/Stop Timing  
SDA  
SCL  
START BIT  
STOP BIT  
5020 FHD F05  
Doc. No. 25060-00 6/99 S-1  
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