Preliminary
CAT24WC128
A.C. CHARACTERISTICS
V
CC
= +1.8V to +6V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol
Parameter
VCC=1.8V - 6.0V VCC=2.5V - 6.0V VCC=3.0V - 5.5V
Min. Max.
Min.
Max.
400
0.9
Min.
Max.
1000
0.55
Units
kHz
µs
FSCL
tAA
Clock Frequency
100
SCL Low to SDA Data Out
and ACK Out
0.1
3.5
0.05
1.2
0.05
0.5
(1)
tBUF
Time the Bus Must be Free Before 4.7
a New Transmission Can Start
µs
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4.0
4.7
4.0
4.0
0.6
1.2
0.6
0.6
0.25
0.6
µs
µs
µs
µs
tHIGH
Clock High Period
0.4
tSU:STA
Start Condition Setup Time
0.25
(for a Repeated Start Condition)
tHD:DAT
tSU:DAT
Data In Hold Time
0
0
0
ns
ns
µs
ns
µs
ns
ms
Data In Setup Time
100
100
100
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
1.0
0.3
0.3
(1)
tF
300
300
100
tSU:STO
tDH
4.7
0.6
50
0.25
50
100
tWR
10
10
10
(1)(2)
Power-Up Timing
Symbol
Parameter
Max.
Units
tPUR
tPUW
Power-Up to Read Operation
Power-Up to Write Operation
1
1
ms
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During
the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave
address.
FUNCTIONAL DESCRIPTION
The CAT24WC128 supports the I2C Bus data transmis-
STOP conditions for bus access. The CAT24WC128
sion protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a re-
ceiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated.
Doc. No. 25060-00 6/99 S-1
3
CATALYST [ CATALYST SEMICONDUCTOR ]
