CAT25C32/64
Advanced Information
Figure 1. Sychronous Data Timing
t
CS
VIH
CS
VIL
t
CSH
t
CSS
VIH
VIL
t
t
WL
SCK
SI
WH
t
t
H
SU
VIH
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
Note: Dashed Line= mode (1, 1) — — — —
A.C. CHARACTERISTICS
Limits
VCC
2.5V-6.0V
Min. Max. Min. Max. Min. Max. UNITS Conditions
Vcc=
1.8V-6.0V
=
VCC
4.5V-5.5V
=
Test
SYMBOL PARAMETER
tSU
tH
Data Setup Time
Data Hold Time
50
50
50
50
20
20
40
40
DC
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
tWH
tWL
fSCK
tLZ
SCK High Time
250
250
DC
125
125
DC
SCK Low Time
Clock Frequency
HOLD to Output Low Z
Input Rise Time
1
50
2
3
50
2
10
50
2
(1)
tRI
CL = 50pF
(1)
tFI
Input Fall Time
2
2
2
tHD
HOLD Setup Time
HOLD Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
100
100
100
100
40
40
tCD
tWC
tV
10
10
5
250
250
80
tHO
tDIS
tHZ
0
0
0
250
150
250
100
75
50
tCS
500
500
500
250
250
250
200
100
100
tCSS
tCSH
NOTE:
CS Setup Time
CS Hold Time
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc No. 25087 -00 8/99 SPI-1
3
CATALYST [ CATALYST SEMICONDUCTOR ]
