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24C01BUA-1.8TE13 参数 Datasheet PDF下载

24C01BUA-1.8TE13图片预览
型号: 24C01BUA-1.8TE13
PDF下载: 下载PDF文件 查看货源
内容描述: [EEPROM, 128X8, Serial, CMOS, PDSO8, TSSOP-8]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件页数/大小: 7 页 / 65 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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CAT24C01B  
SDA: Serial Data/Address  
FUNCTIONAL DESCRIPTION  
The CAT24C01B bidirectional serial data/address pin is  
usedtotransferdataintoandoutofthedevice. TheSDA  
pin is an open drain output and can be wired with other  
open drain or open collector outputs.  
The CAT24C01B uses a 2-wire data transmission pro-  
tocol. Theprotocoldefinesanydevicethatsendsdatato  
thebustobeatransmitterandanydevicereceivingdata  
tobeareceiver. DatatransferiscontrolledbytheMaster  
device which generates the serial clock and all START  
and STOP conditions for bus access. The CAT24C01B  
operates as a Slave device. Both the Master and Slave  
devicescanoperateaseithertransmitterorreceiver,but  
the Master device controls which mode is activated.  
2-WIRE BUS PROTOCOL  
The following defines the features of the 2-wire bus  
protocol:  
(1) Data transfer may be initiated only when the bus is  
not busy.  
PIN DESCRIPTIONS  
(2) During a data transfer, the data line must remain  
stable whenever the clock line is high. Any changes  
in the data line while the clock line is high will be  
interpreted as a START or STOP condition.  
SCL: Serial Clock  
The CAT24C01B serial clock input pin is used to clock  
alldatatransfersintooroutofthedevice. Thisisaninput  
pin.  
Figure 1. Bus Timing  
t
t
t
F
HIGH  
R
t
t
LOW  
LOW  
SCL  
t
t
SU:STA  
HD:DAT  
t
t
t
t
HD:STA  
SU:DAT  
SU:STO  
BUF  
SDA IN  
t
t
AA  
DH  
SDA OUT  
5020 FHD F03  
Figure 2. Write Cycle Timing  
SCL  
SDA  
8TH BIT  
BYTE n  
ACK  
t
WR  
STOP  
CONDITION  
START  
CONDITION  
ADDRESS  
5020 FHD F04  
Figure 3. Start/Stop Timing  
SDA  
SCL  
5020 FHD F05  
START BIT  
STOP BIT  
Doc. No. 25085-00 7/99 S-1  
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