BSI
BS616LV2015
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
V
DR ≥ 1.5V
Vcc
Vcc
t
Vcc
R
t
CDR
≥
CE Vcc - 0.2V
VIH
VIH
CE
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
Input Pulse Levels
Vcc/0V
5ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
Input and Output
MUST BE
STEADY
MUST BE
STEADY
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
AC TEST LOADS AND WAVEFORMS
FROM H TO L
Ω
Ω
1928
1928
5PF
MAY CHANGE
FROM L TO H
WILL BE
5.0V
5.0V
CHANGE
OUTPUT
OUTPUT
FROM L TO H
,
DON T CARE:
CHANGE :
STATE
100PF
INCLUDING
INCLUDING
ANY CHANGE
PERMITTED
Ω
Ω
1020
1020
JIG AND
SCOPE
JIG AND
SCOPE
UNKNOWN
DOES NOT
APPLY
CENTER
FIGURE 1A
FIGURE 1B
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
THEVENIN EQUIVALENT
667
Ω
OUTPUT
1.73V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
→
←
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 5.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
BS616LV2015-70
MIN. TYP. MAX.
BS616LV2015-55
MIN. TYP. MAX.
PARAMETER
NAME
DESCRIPTION
UNIT
tAVAX
tAVQV
tELQV
tBA
tGLQV
tELQX
tBE
tGLQX
tEHQZ
tBDO
tRC
Read Cycle Time
70
--
--
--
--
--
--
--
--
--
--
--
--
--
55
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
30
30
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
tACS
Address Access Time
70
70
35
35
--
Chip Select Access Time
(CE)
(LB,UB)
--
--
--
--
--
--
(1)
tBA
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
tOE
tCLZ
tBE
tOLZ
tCHZ
tBDO
tOHZ
(CE)
(LB,UB)
10
10
10
0
0
0
10
10
10
0
0
0
--
--
35
35
30
--
--
30
30
25
(CE)
(LB,UB)
tGHQZ
tAXOX
tOH
Output Disable to Address Change
10
--
--
10
--
--
ns
NOTE :
1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle. ; tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle.
Revision 2.5
April 2002
R0201-BS616LV2015
4
BSI [ BRILLIANCE SEMICONDUCTOR ]
