BSI
BS616LV1010
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
V
DR ≥ 1.5V
Vcc
Vcc
t
Vcc
R
t
CDR
≥
CE Vcc - 0.2V
VIH
VIH
CE
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
Input Pulse Levels
Vcc/0V
5ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
Input and Output
MUST BE
STEADY
MUST BE
STEADY
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
AC TEST LOADS AND WAVEFORMS
FROM H TO L
Ω
Ω
1269
1269
5PF
MAY CHANGE
FROM L TO H
WILL BE
3.3V
3.3V
CHANGE
OUTPUT
OUTPUT
FROM L TO H
,
DON T CARE:
CHANGE :
STATE
100PF
INCLUDING
INCLUDING
ANY CHANGE
PERMITTED
Ω
Ω
1404
1404
JIG AND
SCOPE
JIG AND
SCOPE
UNKNOWN
DOES NOT
APPLY
CENTER
FIGURE 1A
FIGURE 1B
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
THEVENIN EQUIVALENT
667
Ω
OUTPUT
1.73V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
→
←
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 3.0V )
READ CYCLE
JEDEC
PARAMETER
BS616LV1010-70
MIN. TYP. MAX.
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
UNIT
NAME
tRC
tAVAX
tAVQV
t E1LQV
tBA
tGLQV
t E1LQX
tBE
tGLQX
tE1HQZ
tBDO
70
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
40
50
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
tACS
tBA
tOE
tCLZ
tBE
tOLZ
tCHZ
tBDO
tOHZ
Address Access Time
Chip Select Access Time
(CE)
(LB,UB)
--
--
--
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
(CE)
(LB,UB)
10
10
10
0
0
0
--
--
35
30
30
(CE)
(LB,UB)
tGHQZ
tAXOX
tOH
Output Disable to Output Address Change
10
--
--
ns
Revision 2.2
April 2001
R0201-BS616LV1010
4
BSI [ BRILLIANCE SEMICONDUCTOR ]
