BSI
BH616UV8010
n DATA RETENTION CHARACTERISTICS (TA = -25OC to +85OC)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP. (1)
MAX.
UNITS
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
VDR
VCC for Data Retention
1.0
--
--
V
0.5
2.5
3.0
12
VCC=1.0V
VCC=2.0V
(3)
ICCDR
Data Retention Current
--
0
uA
Chip Deselect to Data
Retention Time
tCDR
tR
1. TA=25OC.
--
--
--
--
ns
ns
See Retention Waveform
(2)
Operation Recovery Time
tRC
2. tRC = Read Cycle Time.
3. ICCDR(MAX.) is 2.5uA /10uA at VCC=1.0V/2.0V and TA=0OC ~ 70OC.
n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
V
DR≧1.0V
VCC
VCC
VCC
tCDR
tR
CE1≧VCC - 0.2V
VIH
VIH
CE1
n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
V
DR≧1.0V
VCC
VCC
VCC
tCDR
tR
CE2≦0.2V
CE2
VIL
VIL
n AC TEST CONDITIONS
n KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
Input Pulse Levels
VCC / 0V
1V/ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
MUST BE
STEADY
MUST BE
STEADY
Input and Output Timing
Reference Level
0.5Vcc
tCLZ1, tCLZ2, tBE, tOLZ, tCHZ1
tCHZ2, tBDO, tOHZ, tWHZ, tOW
,
MAY CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “H” TO “L”
CL = 5pF+1TTL
CL = 30pF+1TTL
Output Load
Others
MAY CHANGE
WILL BE CHANGE
FROM “L” TO “H”
FROM “L” TO “H”
ALL INPUT PULSES
DON’T CARE
ANY CHANGE
PERMITTED
VCC
CHANGE :
STATE UNKNOW
1 TTL
90%
90%
Output
10%
10%
GND
(1)
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
®
¬
®
¬
CL
DOES NOT
APPLY
Rise Time:
1V/ns
Fall Time:
1V/ns
1. Including jig and scope capacitance.
R0201-BH616UV8010
Revision 1.0
Jul. 2005
4
BSI [ BRILLIANCE SEMICONDUCTOR ]
