BH616UV8011
DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)
SYMBOL
VDR
PARAMETER
VCC for Data Retention
Data Retention Current
TEST CONDITIONS
MIN.
1.0
--
TYP. (1)
MAX.
UNITS
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
--
1.2
--
--
7.0
--
V
ICCDR
tCDR
uA
ns
ns
VCC=1.2V
Chip Deselect to Data
Retention Time
0
See Retention Waveform
(2)
tR
Operation Recovery Time
tRC
--
--
1. Typical characteristics are at TA=25OC and not 100% tested.
2. tRC = Read Cycle Time.
LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
DR≧1.0V
V
VCC
tCDR
VCC
tR
VCC
CE1≧VCC - 0.2V
VIH
VIH
CE1
LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
VDR≧1.0V
VCC
tCDR
VCC
tR
VCC
CE2≦0.2V
CE2
VIL
VIL
AC TEST CONDITIONS
KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
WAVEFORM
INPUTS
OUTPUTS
Input Pulse Levels
VCC / 0V
1V/ns
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
Input and Output Timing
Reference Level
0.5Vcc
MAY CHANGE
WILL BE CHANGE
FROM “H” TO “L”
tCLZ1, tCLZ2, tBE, tOLZ, tCHZ1
,
FROM “H” TO “L”
CL = 5pF+1TTL
CL = 30pF+1TTL
tCHZ2, tBDO, tOHZ, tWHZ, tOW
Output Load
MAY CHANGE
WILL BE CHANGE
FROM “L” TO “H”
Others
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
ALL INPUT PULSES
CHANGE :
STATE UNKNOW
VCC
1 TTL
90%
90%
Output
10%
10%
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
GND
DOES NOT
APPLY
(1)
→
←
→
←
CL
Rise Time:
Fall Time:
1V/ns
1V/ns
1. Including jig and scope capacitance.
Revision
Oct.
1.2
2008
R0201-BH616UV8011
4
BSI [ BRILLIANCE SEMICONDUCTOR ]
