ADS7863
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SBAS383–JUNE 2007
TIMING CHARACTERISTICS (continued)
CLOCK
Cycle 1
TBD
Cycle 2
TBD
12ns
12ns
CONVST
A
B
C
NOTE: All CONVST commands that occur more than 12ns before the rising edge of cycle ‘1’ of the external clock
(Region ‘A’) initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands that occur TBDns after the
rising edge of cycle ‘1’ or 12ns before the rising edge of cycle 2 (Region ‘B’) initiate a conversion on the rising edge
of cycle ‘2’. All CONVST commands that occur TBDns after the rising edge of cycle ‘2’ (Region ‘C’) initiate a
conversion on the rising edge of the next clock period.
The CONVST pin should never be switched from LOW to HIGH in the region 12ns prior to the rising edge of the
CLOCK and TBDns after the rising edge (gray areas). If CONVST is toggled in this gray area, the conversion could
begin on either the same rising edge of the CLOCK or the following edge.
Figure 2. CONVST Timing
TIMING REQUIREMENTS(1)
Over recommended operating free-air temperature range at –40°C to +125°C, AVDD = 5V, and BVDD = 2.7V to 5V, unless
otherwise noted.
ADS7863
SYMBOL
PARAMETER
Conversion time
COMMENTS
fCLOCK = 24MHz
MIN
541.67
125
1
MAX
UNIT
ns
tCONV
tACQ
fCLOCK
TCLOCK
tCKL
tCKH
t1
Acquisition time
fCLOCK = 24MHz
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
ns
CLOCK frequency
24
MHz
ns
CLOCK period
41.67
5
1000
CLOCK low time
ns
CLOCK high time
5
ns
CONVST high time
15
ns
t2
SDI setup time to CLOCK falling edge
SDI hold time to CLOCK falling edge
RD high setup time to CLOCK falling edge
RD high hold time to CLOCK falling edge
CONVST low time
10
ns
t3
5
ns
t4
10
ns
t5
5
ns
t6
15
ns
t7
RD low time relative to CLOCK falling edge
CS low to SDOx valid
15
ns
t8
20
ns
SDOx data setup time to CLOCK falling
edge
t9
See Figure 1
25
ns
ns
ns
t10
t11
SDOx data hold time to CLOCK falling edge See Figure 1
5
CONVST setup time to rising edge of
See Figure 1
CLOCK
12
t12
t13
CLOCK rising edge to BUSY low delay
CS low to RD high delay
See Figure 1
See Figure 1
3
ns
ns
10
(1) All input signals are specified with tR = tF = 1.5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2.
8
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