The reference current diminishes directly with both conver-
sion rate and reference voltage. As the current from the
reference is drawn on each bit decision, clocking the con-
verter more quickly during a given conversion period will
not reduce the overall current drain from the reference. The
reference current changes only slightly with temperature.
See the curves, “Reference Current vs Sample Rate” and
“Reference Current vs Temperature” in the Typical Perfor-
mance Curves section for more information.
value for one clock period. For the next 12 DCLOCK
periods, DOUT will output the conversion result, most sig-
nificant bit first. After the least significant bit (B0) has been
output, subsequent clocks will repeat the output data but in
a least significant bit first format.
After the most significant bit (B11) has been repeated, DOUT
will tri-state. Subsequent clocks will have no effect on the
converter. A new conversion is initiated only when CS has
been taken HIGH and returned LOW.
DIGITAL INTERFACE
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
SERIAL INTERFACE
tSMPL
tCONV
tCYC
Analog Input Sample TIme
Conversion Time
1.5
2.0
Clk Cycles
Clk Cycles
kHz
12
The ADS7816 communicates with microprocessors and other
digital systems via a synchronous 3-wire serial interface as
shown in Figure 1 and Table I. The DCLOCK signal
synchronizes the data transfer with each bit being transmit-
ted on the falling edge of DCLOCK. Most receiving systems
will capture the bitstream on the rising edge of DCLOCK.
However, if the minimum hold time for DOUT is acceptable,
the system can use the falling edge of DCLOCK to capture
each bit.
Throughput Rate
200
0
tCSD
CS Falling to
DCLOCK LOW
ns
tSUCS
thDO
tdDO
CS Falling to
DCLOCK Rising
30
15
ns
ns
ns
DCLOCK Falling to
Current DOUT Not Valid
DCLOCK Falling to Next
DOUT Valid
85
150
tdis
ten
CS Rising to DOUT Tri-State
25
50
50
ns
ns
A falling CS signal initiates the conversion and data transfer.
The first 1.5 to 2.0 clock periods of the conversion cycle are
used to sample the input signal. After the second falling
DCLOCK edge, DOUT is enabled and will output a LOW
DCLOCK Falling to DOUT
Enabled
100
tf
tr
DOUT Fall Time
DOUT Rise Time
70
60
100
100
ns
ns
TABLE I. Timing Specifications –40°C to +85°C.
tCYC
CS/SHDN
POWER
DOWN
tSUCS
DCLOCK
tCSD
NULL
BIT
NULL
BIT
HI-Z
HI-Z
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0(1)
B11 B10 B9 B8
DOUT
(MSB)
tSMPL
tCONV
tDATA
Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output LSB-First data then followed with zeroes indefinitely.
tCYC
CS/SHDN
DCLOCK
DOUT
tSUCS
POWER DOWN
tCSD
NULL
HI-Z
HI-Z
BIT
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
(2)
(MSB)
tSMPL
tCONV
tDATA
Note: (2) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output zeroes indefinitely.
tDATA: During this time, the bias current and the comparator power down and the reference input
becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.
FIGURE 1. ADS7816 Basic Timing Diagrams.
®
9
ADS7816
BB [ BURR-BROWN CORPORATION ]
