to a 12-bit settling level within 1.5 clock cycles. When the
converter goes into the hold mode or while it is in the power
down mode, the input impedance is greater than 1GΩ.
THEORY OF OPERATION
The ADS7816 is a classic successive approximation register
(SAR) analog-to-digital (A/D) converter. The architecture is
based on capacitive redistribution which inherently includes
a sample/hold function. The converter is fabricated on a 0.6µ
CMOS process. The architecture and process allow the
ADS7816 to acquire and convert an analog signal at up to
200,000 conversions per second while consuming very little
power.
Care must be taken regarding the absolute analog input
voltage. To maintain the linearity of the converter, the –In
input should not exceed GND ±200mV. The +In input
should always remain within the range of GND –200mV to
VCC +200mV. Outside of these ranges, the converter’s lin-
earity may not meet specifications.
The ADS7816 requires an external reference, an external
clock, and a single +5V power source. The external refer-
ence can be any voltage between 100mV and VCC. The value
of the reference voltage directly sets the range of the analog
input. The reference input current depends on the conversion
rate of the ADS7816.
REFERENCE INPUT
The external reference sets the analog input range. The
ADS7816 will operate with a reference in the range of 100mV
to VCC. There are several important implications of this.
As the reference voltage is reduced, the analog voltage
weight of each digital output code is reduced. This is often
referred to as the LSB (least significant bit) size and is equal
to the reference voltage divided by 4096. This means that
any offset or gain error inherent in the A/D converter will
appear to increase, in terms of LSB size, as the reference
voltage is reduced. The typical performance curves of
“Change in Offset vs Reference Voltage” and “Change in
Gain vs Reference Voltage” provide more information.
The external clock can vary between 10kHz (625Hz through-
put) and 3.2MHz (200kHz throughput). The duty cycle of
the clock is essentially unimportant as long as the minimum
high and low times are at least 150ns. The minimum clock
frequency is set by the leakage on the capacitors internal to
the ADS7816.
The analog input is provided to two input pins: +In and –In.
When a conversion is initiated, the differential input on these
pins is sampled on the internal capacitor array. While a
conversion is in progress, both inputs are disconnected from
any internal function.
The noise inherent in the converter will also appear to
increase with lower LSB size. With a 5V reference, the
internal noise of the converter typically contributes only
0.16 LSB peak-to-peak of potential error to the output code.
When the external reference is 100mV, the potential error
contribution from the internal noise will be 50 times larger—
8 LSBs. The errors due to the internal noise are gaussian in
nature and can be reduced by averaging consecutive conver-
sion results.
The digital result of the conversion is clocked out by the
DCLOCK input and is provided serially, most significant bit
first, on the DOUT pin. The digital data that is provided on the
DOUT pin is for the conversion currently in progress—there
is no pipeline delay. It is possible to continue to clock the
ADS7816 after the conversion is complete and to obtain the
serial data least significant bit first. See the Digital Interface
section for more information.
For more information regarding noise, consult the typical
performance curves “Effective Number of Bits vs Reference
Voltage” and “Peak-to-Peak Noise vs Reference Voltage.”
The effective number of bits (ENOB) figure is calculated
based on the converter’s signal-to-(noise + distortion) ratio
with a 1kHz, 0dB input signal. SINAD is related to ENOB
as follows: SINAD = 6.02 • ENOB +1.76.
ANALOG INPUT
The +In and –In input pins allow for a differential input signal.
Unlike some converters of this type, the –In input is not re-
sampled later in the conversion cycle. When the converter
goes into the hold mode, the voltage difference between +In
and –In is captured on the internal capacitor array.
With lower reference voltages, extra care should be taken to
provide a clean layout including adequate bypassing, a clean
power supply, a low-noise reference, and a low-noise input
signal. Because the LSB size is lower, the converter will also
be more sensitive to external sources of error such as nearby
digital signals and electromagnetic interference.
The range of the –In input is limited to ±200mV. Because of
this, the differential input can be used to reject only small
signals that are common to both inputs. Thus, the –In input
is best used to sense a remote signal ground that may move
slightly with respect to the local ground potential.
The current that must be provided by the external reference
will depend on the conversion result. The current is lowest
at full-scale (FFFh) and is typically 25µA at a 200kHz
conversion rate (25°C). For the same conditions, the current
will increase as the input approaches zero, reaching 50µA at
an output result of 000h. The current does not increase
linearly, but depends, to some degree, on the bit pattern of
the digital output.
The input current on the analog inputs depends on a number
of factors: sample rate, input voltage, source impedance, and
power down mode. Essentially, the current into the ADS7816
charges the internal capacitor array during the sample pe-
riod. After this capacitance has been fully charged, there is
no further input current. The source of the analog input
voltage must be able to charge the input capacitance (25pF)
®
ADS7816
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BB [ BURR-BROWN CORPORATION ]
