PIN #
NAME
DESCRIPTION
1
2
3
VIN
GND
REF
Analog Input. Full-scale input range is ±2.5V.
Ground.
Reference Input/Output. Outputs internal reference of +2.5V nominal. Can also be driven by external system reference. In
both cases, connect to ground with a 0.1µF ceramic capacitor in parallel with 2.2µF tantalum capacitor.
Reference compensation capacitor. Use a parallel combination of a 0.1µF ceramic capacitor and a 2.2µF tantalum capacitor.
Ground.
Data Bit 15. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, when R/C is LOW or when a
conversion is in progress.
4
5
6
CAP
GND
D15 (MSB)
7
8
9
D14
D13
D12
D11
D10
D9
D8
GND
D7
D6
D5
D4
D3
Data Bit 14. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 13. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 12. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 11. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 10. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 9. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 8. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Ground.
Data Bit 7. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 6. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 5. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 4. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 3. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 2. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 1. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 0. Least Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, when R/C is LOW or when a
conversion is in progress.
10
11
12
13
14
15
16
17
18
19
20
21
22
D2
D1
D0 (LSB)
23
24
–VS
R/C
Negative supply input. Nominally –5V. Decouple to analog ground with 0.1µF ceramic and 10µF tantalum capacitors.
Read/convert input. With R/C HIGH, CS going LOW will enable the output data bits if a conversion is not in progress. With
R/C LOW, CS going LOW will start a conversion if one is not already in progress.
Chip select. With R/C LOW, CS going LOW will initiate a conversion if one is not already in progress. With R/C HIGH, CS
going LOW will enable the output data bits if a conversion is not in progress.
Busy output. Falls when a conversion is started, and remains LOW until the conversion is completed. With CS LOW and
R/C HIGH, output data will be valid when BUSY rises, so that the rising edge can be used to latch the data. CS or R/C must
be HIGH within 250ns after BUSY rises or another conversion will start without time for signal acquisition.
Positive supply input. Nominally +5V. Connect directly to pin 28.
25
26
CS
BUSY
27
28
+VS
+VS
Positive supply input. Nominally +5V. Connect directly to pin 27. Decouple to ground with 0.1µF ceramic and 10µF
tantalum capacitors.
TABLE I. Pin Assignments.
PIN CONFIGURATION
Top View
SOIC
1
2
3
4
5
6
7
8
9
28
+VS
VIN
GND
27 +VS
26 BUSY
25 CS
24 R/C
23 –VS
22 D0 (LSB)
21 D1
REF
CAP
GND
D15 (MSB)
D14
ADS7811
D13
D12
20 D2
D11 10
D10 11
D9 12
19 D3
18 D4
17 D5
D8 13
16 D6
GND 14
15 D7
®
4
ADS7811
BB [ BURR-BROWN CORPORATION ]
