THEORY OF OPERATION
+5V
1
2
3
4
5
6
7
8
9
IN 1
IN 2
REF
+5V 24
+5V 23
–15V
The ADS7800 combines the advantages of advanced CMOS
technology (logic density, stable capacitors, and good
analog switches) with Burr-Brown’s proven skills in laser-
trimmed thin-film resistors to provide a complete sampling
A/D converter.
+
6.8µF
1µF
0.1µF
Input
47µF
22
+
+
–15V
AGND BUSY 21
D11 (MSB) CS 20
Busy
A basic charge-redistribution successive approximation
architecture converts analog input voltages into digital
words. Figure 1 shows the operation of a simplified three
bit charge redistribution A/D. Precision laser-trimmed
scaling resistors at the input divide standard input ranges
(±10V or ±5V for the ADS7800) into levels compatible with
the CMOS characteristics of the internal capacitor array.
D10
D9
R/C 19
HBE 18
D0 (LSB) 17
D1 16
Convert
Command
D8
D7
While in the sampling mode, the capacitor array switch for
the MSB capacitor (S1) is in position “S”, so that the charge
on the MSB capacitor is proportional to the voltage level of
the analog input signal, and the remaining array switches (S2
and S3) are set to position “R” to provide an accurate bipolar
offset from the reference source REF. At the same time,
switch SC is also in the closed position to auto-zero any
offset errors in the CMOS comparator.
10 D6
11 D5
12 D4
D2 15
D3 14
DGND 13
D11
(MSB)
D0
(LSB)
Data Out
When a convert command is received, switch S1 is opened
to trap a charge on the MSB capacitor proportional to the
input level at the time of the sampling command, switches
S2 and S3 are opened to trap an offset charge, and switch
SC is opened to float the comparator input. The charge
trapped on the capacitor array can now be moved between
the three capacitors in the array by connecting switches S1,
S2 and S3 to positions “R” (to connect to REF) or “G” (to
connect to GND) successively, changing the voltage gener-
ated at the comparator input node.
FIGURE 2. Basic ±10V Operation.
OPERATION
BASIC OPERATION
Figure 2 shows the simple hookup circuit required to operate
the ADS7800 in a ±10V range in the Convert Mode. A
convert command arriving on pin 19, R/C, (a pulse taking
pin 19 LOW for a minimum of 40ns) puts the ADS7800 in
the hold mode, and a conversion is started. Pin 21, BUSY,
will be held LOW during the conversion, and rises only after
the conversion is completed and the data has been trans-
ferred to the output latches. Thus, the rising edge of the
signal on pin 21 can be used to read the data from the
conversion. Also, during conversion, the BUSY signal puts
the output data lines in Hi-Z states and inhibits input lines.
This means that pulses on pin 19 are ignored, so that new
conversions cannot be initiated during a conversion, either
as a result of spurious signals or to short-cycle the
ADS7800.
The first approximation connects the MSB capacitor via
switch S1 to REF, while switches S2 and S3 are connected
to GND. Depending on whether the comparator output is
HIGH or LOW, the logic will then latch S1 in position “R”
or “G”, and moves on to make the next approximation by
connecting S2 to REF and S3 to GND. When the three
successive approximation steps are made for this simple
converter, the voltage level at the comparator will be within
1/2LSB of GND, and the data output word will be based on
reading the positions of S1, S2 and S3.
In the Read Mode, the input to pin 19 is kept normally LOW,
and a HIGH pulse is used to read data and initiate a
conversion. In this mode, the rising edge of R/C on pin 19
will enable the output data pins, and the data from the
previous conversion becomes valid. The falling edge then
puts the ADS7800 in a hold mode, and initiates a new
conversion.
Comparator
To Switches
SC
L
o
g
i
Input
Signal
Out
4C
2C
R
C
S
c
S1
G
S2
G
S3
G
R
R
The ADS7800 will begin acquiring a new sample as soon
as the conversion is completed, even before the BUSY
output rises on pin 21, and will track the input signal until
the next conversion is started, whether in the Convert Mode
or the Read Mode.
+
Ref
–
FIGURE 1. 3-Bit Charge Redistribution A/D.
®
7
ADS7800
BB [ BURR-BROWN CORPORATION ]
