S/H CONTROL MODE
AND ADC574 EMULATION MODE
tHRL
R/C
The basic difference between these two modes is the
assumptions about the state of the input signal both before
and during the conversion. The differences are shown in
Figure 9 and Table VI. In the Control Mode it is assumed
that during the required 4µs acquisition time the signal is not
slewing faster than the slew rate of the ADS574. No
assumption is made about the input level after the convert
command arrives, since the input signal is sampled and
conversion begins immediately after the convert command.
tDS
Status
tC
tHDR
tHS
High-Z-State
DB11-DB0
Data Valid
Data Valid
FIGURE 3. R/C Pulse Low—OutputsEnabled AfterConver-
sion.
This means that a convert command can also be used to
switch an input multiplexer or change gains on a program-
mable gain amplifier, allowing the input signal to settle
before the next acquisition at the end of the conversion.
Because aperture jitter is minimized by the internal sample/
hold circuit, a high input frequency can be converted without
an external sample/hold.
R/C
tHRH
tDS
Status
In the Emulation Mode, no assumption is made about the
input signal prior to the convert command. A delay time is
introduced between the convert command and the start of
conversion to allow the ADS574 enough time to acquire the
input signal before converting. The delay increases the
effective aperture time from 0.02µs to 4µs, but allows the
ADS574 to replace the ADC574 in any circuit. Any slewing
of the analog input prior to the convert command in existing
tC
tDDR
tHDR
High-Z
DB11-DB0
High-Z-State
Data Valid
FIGURE 4. R/C Pulse High — Outputs Enabled Only While
R/C Is High.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
tHRL
tDS
tHDR
tHRH
tDDR
Low R/C Pulse Width
STS Delay from R/C
Data Valid After R/C Low
High R/C Pulse Width
Data Access Time
25
ns
ns
ns
ns
ns
200
25
100
150
TABLE IV. Stand-Alone Mode Timing. (TA = TMIN to TMAX ).
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
Convert Mode
tDSC
STS delay from CE
CE Pulse width
CS to CE setup
CS low during CE high
R/C to CE setup
R/C low during CE high
AO to CE setup
60
30
20
20
0
200
ns
ns
ns
ns
ns
ns
ns
ns
tHEC
tSSC
tHSC
tSRC
tHRC
tSAC
tHAC
50
50
50
50
50
0
20
AO valid during CE high
50
20
Read Mode
tDD
Access time from CE
Data valid after CE low
Output float delay
CS to CE setup
R/C to CE setup
75
35
100
0
150
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHD
tHL
tSSR
tSRR
tSAR
tHSR
tHRR
tHAR
tHS
25
50
0
50
0
0
50
300
AO to CE setup
25
CS valid after CE low
R/C high after CE low
AO valid after CE low
STC delay after data valid
400
1000
TABLE V. Timing Specifications, Fully Controlled Operation. (TA = TMIN to TMAX ).
®
9
ADS574
BB [ BURR-BROWN CORPORATION ]
