Binary (BIN) Output
Input Voltage Range and LSB Values
Analog Input Voltage Range
Defined As:
±10V
+5V
0V to +10V
0V to +20V
One Least Significant Bit
(LSB)
FSR
2n
20V
2n
10V
2n
10V
2n
20V
2n
n = 8
n = 12
78.13mV
4.88mV
39.06mV
2.44mV
39.06mV
2.44mV
78.13mV
4.88mV
Output Transition Values
FFEH to FFFH
7FFFH to 800H
+ Full-Scale Calibration
Midscale Calibration (Bipolar Offset)
Zero Calibration ( – Full-Scale Calibration)
+10V – 3/2LSB
0 – 1/2LSB
–10V + 1/2LSB
+5V – 3/2LSB
0 – 1/2LSB
–5V + 1/2LSB
+10V – 3/2LSB
+5V – 1/2LSB
0 to +1/2LSB
+10V – 3/2LSB
±10V – 1/2LSB
0 to +1/2LSB
000H to 001H
TABLE I. Input Voltages, Transition Values, and LSB Values.
DESIGNATION
DEFINITION
FUNCTION
CE (Pin 6)
Chip Enable
(active high)
Must be HIGH (“1”) to either initiate a conversion or read output data. 0-1 edge may be used to initiate a
conversion.
CS (Pin 3)
R/C (Pin 5)
Chip Select
(active low)
Must be LOW (“0”) to either initiate a conversion or read output data. 1-0 edge may be used to initiate a
conversion.
Read/Convert
(“1” = read)
Must be LOW (“0”) to initiate either 8- or 12-bit conversions. 1-0 edge may be used to initiate a conversion.
Must be HIGH (“1”) to read output data. 0-1 edge may be used to initiate a read operation.
(“0” = convert)
AO (Pin 4)
Byte Address
Short Cycle
In the start-convert mode, AO selects 8-bit (AO = “1”) or 12-bit (AO = “0”) conversion mode. When reading
output data in two 8-bit bytes, AO = “0” accesses 8 MSBs (high byte) and AO = “1” accesses 4 LSBs and
trailing “0s” (low byte).
12/8 (Pin 2)
Data Mode Select
(“1” = 12 bits)
(“0” = 8 bits)
When reading output data, 12/8 = “1” enables all 12 output bits simultaneously. 12/8 = “0” will enable the
MSBs or LSBs as determined by the AO line.
TABLE II. Control Line Functions.
CE
CS
R/C
12/8
AO
OPERATION
0
X
↑
X
1
0
0
↓
X
X
0
0
0
0
↓
↓
X
X
X
X
X
X
X
X
1
X
X
0
1
0
1
0
1
X
0
1
None
None
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Enable 12-bit output
Enable 8 MSBs only
Enable 4 LSBs plus 4
trailing zeroes
↑
1
1
1
1
1
1
1
↓
0
0
0
0
0
1
1
1
0
0
TABLE III. Control Input Truth Table.
READING OUTPUT DATA
When 12/8 is LOW, the data is presented in the form of two
8-bit bytes, with selection of the byte of interest accom-
plished by the state of A0 during the read cycle. When A0 is
LOW, the byte addressed contains the 8MSBs. When A0 is
HIGH, the byte addressed contains the 4LSBs from the
conversion followed by four logic zeros which have been
forced by the control logic. The left-justified formats of the
two 8-bit bytes are shown in Figure 7. Connection of the
ADS574 to an 8-bit bus for transfer of the data is illustrated
in Figure 8. The design of the ADS574 guarantees that the
A0 input may be toggled at any time with no damage to the
converter; the outputs which are tied together in Figure 8
cannot be enabled at the same time. The A0 input is usually
driven by the least significant bit of the address bus, allow-
ing storage of the output data word in two consecutive
memory locations.
After conversion is initiated, the output data buffers remain
in a high-impedance state until the following four logic
conditions are simultaneously met: R/C HIGH, STATUS
LOW, CE HIGH, and CS LOW. Upon satisfaction of these
conditions the data lines are enabled according to the state of
inputs 12/8 and A0. See Figure 6 and Table V for timing
relationships and specifications.
In most applications the 12/8 input will be hard-wired in
either the high or low condition, although it is fully TTL and
CMOS-compatible and may be actively driven if desired.
When 12/8 is HIGH, all 12 output lines (DB0-DB11) are
enabled simultaneously for full data word transfer to a 12-bit
or 16-bit bus. In this situation the A0 state is ignored when
reading the data.
®
8
ADS574
BB [ BURR-BROWN CORPORATION ]
