TYPICAL CHARACTERISTICS (Cont.)
TA = 25°C, +VSA = +VSD = +5V, differential input range = 1.5V to 3.5V each input (4Vp-p), sampling rate = 40MSPS, internal reference, and VDRV = 3V, unless otherwise
noted.
SWEPT POWER (SNR)
(FIN = 10MHz)
OUTPUT NOISE HISTOGRAM
(DC Common-Mode Input)
700000
600000
500000
400000
300000
200000
100000
0
90
80
70
60
50
40
30
20
10
0
dBc
dBFS
N – 3 N – 2 N – 1
N
N + 1 N + 2 N + 3
–60
–50
–40
–30
–20
–10
0
Code
Input Amplitude (dBFS)
nonlinearity of RON. For ease of use, the ADS5421 incorpo-
rates a selectable voltage reference, a versatile clock input,
and a logic output driver designed to interface to 3V or 5V
logic.
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS5421 is a high-speed, high-performance, CMOS
ADC build with a fully differential pipeline architecture. Each
stage contains a low-resolution quantizer and digital error
correction logic ensuring good differential linearity. The con-
version process is initiated by a rising edge of the external
convert clock. Once the signal is captured by the input track-
and-hold amplifier, the bits are sequentially encoded starting
with the Most Significant Bit (MSB). This process results in a
data latency of 10 clock cycles after which the output data is
available as a 14-bit parallel word either coded in a Straight
Offset Binary or Binary Two’s Complement format.
S5
ADS5421
S3
VBIAS
CIN
CIN
S1
S2
IN
IN
T&H
The analog input of the ADS5421 consists of a differential
track-and-hold circuit, as shown in Figure 1. The differential
topology produces a high level of AC performance at high
sampling rates. It also results in a very high usable input
bandwidth—especially important for Intermediate Frequency
(IF) or undersampling applications. Both inputs (IN, IN)
require external biasing up to a common-mode voltage that
is typically at the mid-supply level (+VS/2). This is because
the on-resistance of the CMOS switches is lowest at this
voltage, minimizing the effects of the signal-dependent,
S4
VBIAS
S6
Tracking Phase: S1, S2, S3, S4 closed; S5, S6 open
Hold Phase: S1, S2, S3, S4 open; S5, S6 closed
FIGURE 1. Simplified Circuit of Input Track-and-Hold Amplifier.
ADS5421
8
SBAS237D
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