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ADS5273IPFP 参数 Datasheet PDF下载

ADS5273IPFP图片预览
型号: ADS5273IPFP
PDF下载: 下载PDF文件 查看货源
内容描述: 8通道, 12位, 70MSPS ADC,具有串行LVDS接口 [8-Channel, 12-Bit, 70MSPS ADC with Serialized LVDS Interface]
分类和应用: 转换器
文件页数/大小: 16 页 / 252 K
品牌: BURR-BROWN [ BURR-BROWN CORPORATION ]
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ADS5273
SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
8-Channel, 12-Bit, 70MSPS ADC
with Serialized LVDS Interface
FEATURES
D
D
D
D
D
D
D
D
Maximum Sample Rate: 70MSPS
12-Bit Resolution
No Missing Codes
Power Dissipation: 1.1W
CMOS Technology
Simultaneous Sample-and-Hold
70.5dB SNR at 10MHz IF
Serialized LVDS Outputs Meet or Exceed the
Requirements of ANSI TIA/EIA-644-A
Standard
PLL
ADCLK
6X ADCLK
LCLK
P
LCLK
N
1X ADCLK
ADCLK
P
ADCLK
N
12−
Bit
ADC
OUT1
P
OUT1
N
OUT2
P
OUT2
N
OUT3
P
OUT3
N
OUT4
P
OUT4
N
OUT5
P
OUT5
N
OUT6
P
OUT6
N
OUT7
P
OUT7
N
OUT8
P
OUT8
N
Registers
Control
The ADS5273 provides an internal reference, or can
optionally be driven with an external reference. Best
performance can be achieved through the internal
reference mode.
The device is available in a PowerPAD TQFP-80 package
and is specified over a −40°C to +85°C operating range.
D
Internal and External References
D
3.3V Digital/Analog Supply
D
TQFP-80 PowerPAD Package
IN1
P
IN1
N
IN2
P
IN2
N
IN3
P
IN3
N
IN4
P
IN4
N
S/H
Serializer
S/H
APPLICATIONS
12−
Bit
ADC
Serializer
D
Portable Ultrasound Systems
D
Tape Drives
D
Test Equipment
S/H
12−
Bit
ADC
Serializer
S/H
12−
Bit
ADC
Serializer
DESCRIPTION
The ADS5273 is a high-performance, 70MSPS, 8-channel
parallel analog-to-digital converter (ADC). An internal
reference is provided, simplifying system design
requirements. Low power consumption allows for the
highest of system integration densities. Serial LVDS
outputs reduce the number of interface lines and package
size.
In LVDS (low-voltage differential signaling), an integrated
phase lock loop multiplies the incoming ADC sampling
clock by a factor of 6. This high-frequency LVDS clock is
used in the data serialization and transmission process
and is converted to an LVDS signal for transmission in
parallel with the data. Providing this additional LVDS clock
allows for easy delay matching. The word output of each
internal ADC is serialized and transmitted either MSB or
LSB first. The bit following the rising edge of the ADC clock
output is the first bit of the word.
IN5
P
IN5
N
IN6
P
IN6
N
IN7
P
IN7
N
IN8
P
IN8
N
S/H
12−
Bit
ADC
Serializer
S/H
12−
Bit
ADC
Serializer
S/H
12−
Bit
ADC
Serializer
S/H
12−
Bit
ADC
Serializer
Reference
CS
SCLK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the formative or design
phase of development. Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or discontinue these
products without notice.
Copyright
2004, Texas Instruments Incorporated
www.ti.com
SDATA
REF
T
V
CM
REF
B
INT/EXT
RESET
PD
PRODUCT PREVIEW