TIMING DIAGRAM
N + 2
N + 1
N + 4
N + 3
Analog In
N + 7
N + 5
N
N + 6
tL
tH
tD
tCONV
Clock
6 Clock Cycles
N – 4 N – 3
t2
Data Out
N – 6
N – 5
N – 2
N – 1
N
N + 1
Data Invalid
t1
t3
Data Valid
t4
SYMBOL
tCONV
tL
DESCRIPTION
MIN
TYP
MAX
UNITS
Convert Clock Period
Clock Pulse Low
31.25
14.6
14.6
100µs
ns
ns
ns
ns
ns
ns
ns
ns
tCONV/2
tCONV/2
2
tH
Clock Pulse High
tD
Aperture Delay
(1)
t1
Data Hold Time, CL = 0pF
2.7
(1)
t2
New Data Delay Time, CL = 15pF max
Data Valid Falling Edge Delay, CL = 15pF max
Data Valid Rising Edge Delay, CL = 15pF max
8.2
7.5
5.6
12
t3
t4
NOTE: (1) t1 and t2 times are valid for VDRV voltages of +2.7V to +5V.
PIN CONFIGURATION
Top View
TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND
GND
+VS
1
2
3
4
5
6
7
8
9
48 GND
47 GND
46 +VS
45 SEL
44 GND
43 +VS
42 OEA
41 GND
GND
+VS
OEB
GND
VDRVB
OVRB
ADS2806Y
40 VDRVA
39 OVRA
38 A1 (MSB)
37 A2
B12 (LSB) 10
B11 11
B10 12
B9 13
36 A3
B8 14
35 A4
B7 15
34 A5
B6 16
33 A6
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ADS2806
SBAS178B
4
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