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SBAS341B − DECEMBER 2004 − REVISED APRIL 2005
TIMING DIAGRAMS
CLK
tSTL
tSYPW
SYNC
FSO
Figure 1. Initialization Timing
TIMING REQUIREMENTS
For T = −40°C to +85°C, DVDD = 2.7V to 3.6V, IOVDD = 2.7V to 5.25V.
A
SYMBOL
DESCRIPTION
MIN
2
TYP
MAX
16
UNIT
t
CLK periods
Conversions
CLK periods
SYNC positive pulse width
SYPW
51
52
(1)
Settling time of ADS1602
t
STL
816
832
:
NOTE (1) An FSO pulse occuring prior to T
≥ 816 CLK period should be ignored.
STL
tCPW
tC
CLK
tCPW
tCF
tFPW
tCS
FSO
SCLK
tDPD
tDHD
DOUT
Bit 0 (LSB)
Bit 15 (MSB)
Bit 14
Bit 1
Bit 0 (LSB)
Old Data
New Data
Figure 2. Data Retrieval Timing
TIMING REQUIREMENTS
For T = −40°C to +85°C, DVDD = 2.7V to 3.6V, IOVDD = 2.7V to 5.25V.
A
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
t
C
25
ns
CLK period (1/f
)
CLK
t
11.25
ns
CLK positive or negative pulse width
CPW
t
15
15
5
ns
Rising edge of CLK to rising edge of FSO
FSO positive pulse width
CF
t
1
CLK period
FPW
t
ns
ns
ns
Rising edge of CLK to rising edge of SCLK
SCLK rising edge to old DOUT invalid (hold time)
SCLK rising edge to new DOUT valid (propagation delay)
CS
t
0
DHD
t
DPD
8
BB [ BURR-BROWN CORPORATION ]
