ADS1212 SIMPLIFIED BLOCK DIAGRAM
AGND AVDD
16
REF OUT
17
REF IN
18
VBIAS
4
XIN
XOUT
8
3
7
+2.5V
Reference
+3.3V Bias
Generator
Clock Generator
9
DGND
10 DVDD
Micro Controller
1
2
AIN
P
Second-Order
∆Σ
Modulator
Instruction Register
Command Register
Data Output Register
Offset Register
Third-Order
Digital Filter
PGA
A
INN
Full-Scale Register
11
SCLK
12
Modulator Control
Serial Interface
SDIO
13
SDOUT
6
5
15
14
DSYNC
CS
MODE DRDY
ADS1212 PIN CONFIGURATION
ADS1212 PIN DEFINITIONS
PIN NO
NAME
AIN
INN
DESCRIPTION
TOP VIEW
DIP/SOIC
1
2
P
Noninverting Input.
Inverting Input.
A
3
AGND
VBIAS
CS
Analog Ground.
4
Bias Voltage Output, +3.3V nominal.
Chip Select Input.
A
INP
1
2
3
4
5
6
7
8
9
18 REFIN
5
AINN
17 REFOUT
16 AVDD
6
DSYNC
XIN
Control Input to Synchronize Serial Output Data.
System Clock Input.
7
AGND
VBIAS
CS
8
XOUT
System Clock Output.
15 MODE
14 DRDY
13 SDOUT
12 SDIO
11 SCLK
10 DVDD
9
DGND
DVDD
SCLK
SDIO
Digital Ground.
ADS1212
10
11
12
Digital Supply, +5V nominal.
Clock Input/Output for serial data transfer.
DSYNC
XIN
Serial Data Input (can also function as Serial Data
Output).
Serial Data Output.
13
14
15
16
17
18
SDOUT
DRDY
MODE
AVDD
XOUT
Data Ready.
SCLK Control Input (Master = 1, Slave = 0).
Analog Supply, +5V nominal.
Reference Output, +2.5V nominal.
Reference Input.
DGND
REFOUT
REFIN
ADS1212, 1213
4
SBAS064A
BB [ BURR-BROWN CORPORATION ]
