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ADS1213E/1KG4 参数 Datasheet PDF下载

ADS1213E/1KG4图片预览
型号: ADS1213E/1KG4
PDF下载: 下载PDF文件 查看货源
内容描述: 22位模拟数字转换器 [22-Bit ANALOG-TO-DIGITAL CONVERTER]
分类和应用: 转换器光电二极管
文件页数/大小: 49 页 / 1227 K
品牌: BB [ BURR-BROWN CORPORATION ]
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SPECIFICATIONS  
All specifications TMIN to TMAX, AVDD = DVDD = +5V, fXIN = 1MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REFOUT disabled, VBIAS disabled,  
and external 2.5V reference, unless otherwise specified.  
ADS1212U, P/ADS1213U, P, E  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
ANALOG INPUT  
Input Voltage Range(1)  
0
–10  
+5  
+10  
V
V
M  
(2)  
With VBIAS  
Input Impedance  
Programmable Gain Amplifier  
Input Capacitance  
G = Gain, TMR = Turbo Mode Rate  
User Programmable: 1, 2, 4, 8, or 16  
20/(G • TMR)(3)  
1
16  
5
5
pF  
pA  
nA  
Input Leakage Current  
At +25°C  
TMIN to TMAX  
50  
1
SYSTEMS PERFORMANCE  
No Missing Codes  
fDATA = 10Hz  
fDATA = 60Hz  
22  
19  
21  
20  
20  
18  
Bits  
Bits  
Bits  
Bits  
Bits  
fDATA = 100Hz, TMR of 4  
fDATA = 250Hz, TMR of 8  
fDATA = 500Hz, TMR of 16  
fDATA = 1000Hz, TMR of 16  
fDATA = 60Hz  
Bits  
Integral Linearity  
±0.0015  
±0.0015  
%FSR  
%FSR  
%FSR  
fDATA = 1000Hz, TMR of 16  
Integral Linearity (Single-Ended)  
Unipolar Offset Error(4)  
Unipolar Offset Drift(6)  
Gain Error(4)  
Gain Error Drift(6)  
Common-Mode Rejection(9)  
0.01  
See Note 5  
1
ppm/°C  
See Note 5  
4
100  
ppm/°C  
dB  
dB  
dB  
dB  
At DC, TMIN to TMAX  
50Hz, fDATA = 50Hz(7)  
60Hz, fDATA = 60Hz(7)  
50Hz, fDATA = 50Hz(7)  
60Hz, fDATA = 60Hz(7)  
90  
160  
160  
100  
100  
Normal-Mode Rejection  
dB  
Output Noise  
See Typical Performance Curves  
Power Supply Rejection  
DC, 50Hz, and 60Hz  
60  
dB  
VOLTAGE REFERENCE  
Internal Reference (REFOUT  
Drift  
Noise  
Load Current  
Output Impedance  
)
2.4  
2.5  
25  
50  
2.6  
1
V
ppm/°C  
µVp-p  
mA  
Source or Sink  
2
External Reference (REFIN  
Load Current  
VBIAS Output  
Drift  
Load Current  
)
2.0  
3.0  
2.5  
3.45  
V
µA  
V
Using Internal Reference  
Source or Sink  
3.15  
3.3  
50  
ppm/°C  
10mA  
DIGITAL INPUT/OUTPUT  
Logic Family  
TTL Compatible CMOS  
Logic Level: (all except XIN  
)
VIH  
VIL  
VOH  
IIH = +5µA  
IIL = +5µA  
IOH = 2 TTL Loads  
IOL = 2 TTL Loads  
2.0  
–0.3  
2.4  
DVDD +0.3  
0.8  
V
V
V
V
V
VOL  
XIN Input Levels: VIH  
VIL  
XIN Frequency Range (fXIN  
Output Data Rate (fDATA  
0.4  
DVDD +0.3  
0.8  
3.5  
–0.3  
0.5  
0.96  
0.48  
2.4  
V
)
2.5  
MHz  
Hz  
Hz  
Hz  
)
User Programmable and TMR = 1 to 16  
fXIN = 500kHz  
6,250  
3,125  
15,625  
fXIN = 2.5MHz  
Data Format  
User Programmable  
Two’s Complement  
or Offset Binary  
SYSTEM CALIBRATION  
Offset and Full-Scale Limits  
VFS – | VOS  
VFS = Full-Scale Differential Voltage(8) 0.7 • (2 • REFIN)/G  
VOS = Offset Differential Voltage(8)  
|
1.3 • (2 • REFIN)/G  
ADS1212, 1213  
2
SBAS064A