measurements, code transition values are the locations actu-
ally measured for this spec. The ideal gain is VFSR –2LSB.
Gain Error is expressed in % (of reading). See Figure 3.
Power Supply Wiring
Use heavy power supply and power supply common (ground)
wiring. A ground plane is usually the best solution for
preserving dynamic performance and reducing noise cou-
pling into sensitive converter circuits.
Gain Error of the ADC700 may be trimmed to zero using
external trim potentiometers.
When passing converter power through a connector, use
every available spare pin for making power supply return
connections, and use some of the pins as a Faraday shield to
separate the analog and digital common lines.
Offset Error
Unipolar Offset Error—The deviation of the actual code-
midpoint value of the first code from the ideal value located
at 1/2LSB below the ideal first transition value (i.e. at zero
volts).
Power Supply Returns
(Analog Common and Digital Common)
Bipolar Offset Error—The deviation of the actual code-
midpoint of the first code from the ideal value located
at 1/2LSB below the ideal first transition value located at –
VFS +1/2LSB.
Connect Analog Common and Digital Common together
right at the converter with the ground plane. This will usually
give the best performance. However, it may cause problems
for the system designer. Where it is absolutely necessary to
separate analog and digital power supply returns, each should
be separately returned to the power supply. Do not connect
Analog Common and Digital Common together and then run
a single wire to the power supply. Connect a 1 to 47µF
tantalum capacitor between Digital Common and Analog
Common pins as close to the package as possible.
Again, transition values are the actual measured parameters.
Offset and Zero errors of the ADC700 may be trimmed to
zero using external trim potentiometers. Offset Error is
expressed as a percentage of FSR.
Bipolar Zero Error—The deviation of the actual mid-
scale-code midpoint value from zero. Transition values are
the actual measured parameter and it is 1/2 LSB below zero
volts. The error is comprised of Bipolar Offset Error, 1/2 the
Gain Error, and the Linearity Error of bit 1. Bipolar Zero
Error is expressed as a percentage of FSR.
Power Supply Bypassing
Every power-supply line leading into an A/D converter must
be bypassed to its common pin. The bypass capacitor should
be located as close to the converter package as possible and
tied to a solid ground—connecting the capacitors to a noisy
ground defeats the purpose of the bypass. Use tantalum
capacitors with values of from 10µF to 100µF and parallel
them with smaller ceramic capacitors for high frequency
filtering if necessary.
Power Supply Sensitivity
Power Supply Sensitivity describes the maximum change in
the full-scale transition value from the initial value for a
change in each power supply voltage. PSR is specified in
units of %FSR/% change in each supply voltage.
The major effect of power supply voltage deviations from
the rated values will be a small change in the Gain (scale
factor). Power Supply Sensitivity is also a function of ripple
frequency. Figure 4 illustrates typical Power Supply Sensi-
tivity performance of ADC700 versus ripple frequency.
Separate Analog and Digital Signals
Digital signals entering or leaving the layout should have
minimum length to minimize crosstalk to analog wiring.
Keep analog signals as far away as possible from digital
signals. If they must cross, cross them at right angles.
Coaxial cable may be necessary for analog inputs in some
situations.
INSTALLATION
POWER SUPPLY SELECTION
Shield Other Sensitive Points
The most critical of these is the comparator input (pin 1). If
this pin is not used for offset adjustment, then it should be
surrounded with ground plane or low-impedance power
Linear power supplies are preferred. Switching power sup-
ply specifications may appear to indicate low noise output,
but these specifications are rms specs. The spikes generated
in switchers may be hard to filter. Their high-frequency
components may be extremely difficult to keep out of the
power supply return system. If switchers must be used, their
outputs must be carefully filtered and the power supply itself
should be shielded and located as far away as possible from
precision analog circuits.
0.1
–VCC
0.01
LAYOUT CONSIDERATIONS
+VCC
+VDD
Because of the high resolution and linearity of the ADC700,
system design problems such as ground path resistance and
contact resistance become very important. For a 16-bit
resolution converter with a +10V Full-Scale Range, 1LSB is
153µV. Circuit situations that cause only second- or third-
order errors in 8-, 10-, or 12-bit A/D converters can induce
first-order errors in 16-bit resolution devices.
0.001
1
10
100
1k
10k
100k
Frequency (Hz)
FIGURE 4. Power Supply Rejection Ripple vs Frequency.
®
7
ADC700
BB [ BURR-BROWN CORPORATION ]
