TWO’S COMPLEMENT DATA CODE
Most Significant Bit, MSB
That binary digit that has the greatest value or weight. The
MSB weight is FSR/2.
BTCEN (pin 23) is a logic function that implements the
Binary Two’s Complement output code for bipolar (+ and –)
analog input signal operation. This feature is compatible
with twos complement arithmetic in microprocessor math
algorithms.
Resolution
An N-bit binary-coded A/D converter resolves the analog
input into 2N values represented by the 2N digital output
codes.
INTERNAL CLOCK
ACCURACY
The ADC700 has a self-contained clock to sequence the
A/D logic. The clock is not available externally. An external
16-pulse strobe (pin 14) is brought out to clock serial data
only. Use of ADC700 with external clock is not possible.
Linearity Error, Integral Linearity Error (ILE)
Linearity Error is defined as the deviation of actual analog
input values from the ideal values about a straight line drawn
through the code mid-points near positive full scale (at +VFS
–1LSB) and at Zero input (at 1/2LSB below the first code
transition, i.e. at Zero) or, in the case of bipolar operation,
near minus full scale (at 1/2LSB below the first code
transition, i.e. at –VFS). Despite the definition, however,
code transitions are easier to measure than code midpoints.
Therefore linearity is measured as the deviation of the
analog input values from a line drawn between the first and
last code transitions. Linearity Error specifications are ex-
pressed in % of Full Scale Range (FSR). ADC700KH ILE
is ±0.003% of FSR which is 1/2 LSB at 14-bits.
INTERNAL VOLTAGE REFERENCE
The ADC700 has an internal low-noise buried-zener voltage
reference. The reference circuit has been drift compensated
over the MIL temperature range using a laser trim algorithm.
The reference voltage is not available externally.
DISCUSSION
OF SPECIFICATIONS
BASIC DEFINITIONS
Differential Linearity Error (DLE), No Missing Codes
Differential Linearity Error is defined as the deviation in
code width from the ideal value of 1LSB. If the DLE is
greater than –1LSB anywhere along the range, the A/D will
have at least one missing code. ADC700KH is specified to
have a DLE of ±0.006% of FSR, which is ±1LSB at 14 bits.
ADC700KH is specified to have no missing codes at the 14-
bit level over specified temperature ranges.
Refer to Figure 3 for an illustration of A/D converter
terminology and to Table II in the Calibration section.
Full Scale Range, FSR
The nominal range of the A/D converter. For ADC700, the
FSR is 20V for the 0V to +20V and the –10V to +10V input
ranges or 10V for the 0V to +10V and –5V to +5V input
ranges.
Gain Error
Least Significant Bit, LSB
The deviation from the ideal magnitude of the input span
between the first code midpoint (at –VFS + 1/2LSB, for
bipolar operation; at Zero for unipolar operation) to the last
code midpoint (VFS –1LSB). As with the linearity error
The smallest analog input change resolved by the A/D
converter. For an A/D converter with N bits output, the input
value of the LSB is FSR(2–N).
5V
FFFH
FFEH
FFDH
802H
Gain
Error
Rotates
The
3kΩ
DBN
DBN
CL
CL
3kΩ
Line
DGND
DGND
801H
800H
7FFH
7FEH
002H
001H
000H
A) High-Z to VOH (t3)
and VOL to VOH (t6).
B) High-Z to VOL (t3)
and VOH to VOL (t6).
Offset Error
Shifts The Line
FIGURE 1. Load Circuits for Access Time.
5V
(Bipolar
Zero
Transition)
Midscale
(Bipolar Zero)
3kΩ
DBN
DBN
3/2LSB
1/2LSB
10pF
10pF
Zero
3kΩ
+Full-Scale
Calibration
Transition
+Full
Scale
Zero
(–Full
Scale)
(–Full-Scale
Calibration
Transition)
1/2LSB
DGND
DGND
Analog Input
A) VOH to High-Z.
B) VOL to High-Z.
FIGURE 2. Load Circuits for Output Float Delay.
FIGURE 3. Transfer Characteristic Terminology.
®
ADC700
6
BB [ BURR-BROWN CORPORATION ]
