TIMING SPECIFICATIONS(6)
At VDD = +5V, +VCC = +12V or +15V, –VCC = –12V or –15V, unless otherwise noted.
LIMIT AT
LIMIT AT
A = 25°C
T
A = 0, +70°C
LIMIT AT
TA = –55°C, +125°C
PARAMETER
T
–25°C, +85°C
UNITS
DESCRIPTION
CONVERSION AND SERIAL DATA OUTPUT TIMING
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
0
110
40
0
15
550
1100
250
310
0
0
130
40
0
17
600
1150
210
360
0
0
145
40
0
17
650
1250
200
400
0
ns, min
ns, max
ns, min
ns, min
µs, max
ns, max
ns, max
ns, min
ns, max
ns, min
CS to WR Setup time
WR to Status delay
WR pulse width
CS to WR Hold time
Conversion time
Data Ready to Status time
WR to first Serial Data Strobe
First Serial Data to first Serial Data Strobe
Last Serial Data Strobe to Status
Status to WR Setup time
PARALLEL DATA OUTPUT TIMING
t11
t12
t13
0
0
50
0
0
58
0
0
66
ns, min
ns, min
ns, max
HBEN to RD Setup time
CS to RD Setup time
High Byte Data Valid after RD
(7)
C
L = 20pF (High Byte bus access time)
High Byte Data Valid after RD
L = 100pF (High Byte bus access time)
70
81
95
ns, max
C
t14
t15
t16
t17
t18
40
40
50
0
40
45
60
0
40
50
65
0
ns, min
ns, max
ns, max
ns, min
ns, min
RD pulse width
Data Ready delay from RD (HBEN asserted)
Data Hold time after RD (bus relinquish time)
RD to CS Hold time
(8)
0
0
0
RD to HBEN Hold time
RESET TIMING
t19
t20
60
70
70
81
80
95
ns, max
ns, max
Data Ready low delay from Reset
Status low delay from Reset
*Same specs as ADC700JH, AH, RH.
NOTES: (1) TTL, LSTTL, and 5V CMOS compatible. (2) FSR means Full Scale Range. For example, unit connected for ±10V range has 20V FSR. (3) Externally
adjustable to zero. (4) See Table I. USB – Unipolar Straight Binary; BTC – Binary Two’s Complement; BOB – Bipolar Offset Binary; NRZ – Non Return to Zero. (5)
Max supply current is specified at rated supply voltages. (6) All input control signals are specified with tRISE = tFALL = 5ns (10% to 90% of 5V) and timed from a voltage
level of 1.6V. (7) t13 is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V. (8) t16 is defined as the time
required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
ABSOLUTE MAXIMUM RATINGS
PACKAGING INFORMATION
PACKAGE DRAWING
NUMBER(1)
+VDD to Digital Common ............................................................ 0V to +7V
+VCC to Analog Common ......................................................... 0V to +18V
–VCC to Analog Common ......................................................... 0V to –18V
Digital Common to Analog Common ........................................ –1V to +1V
Digital Inputs to Digital Common................................ –0.5V to VDD + 0.5V
Analog Inputs .................................................................................. +16.5V
Power Dissipation ........................................................................ 1000mW
Storage Temperature ...................................................... –60°C to +150°C
Lead Temperature, (soldering, 10s) ............................................... +300°C
MODEL
PACKAGE
ADC700JH
ADC700KH
ADC700AH
ADC700BH
ADC700RH
ADC700SH
28-Pin Ceramic DIP
28-Pin Ceramic DIP
28-Pin Ceramic DIP
28-Pin Ceramic DIP
28-Pin Ceramic DIP
28-Pin Ceramic DIP
237
237
237
237
237
237
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
NOTES: Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maxi-
mum rating conditions for extended periods may affect device reliability.
ORDERING INFORMATION
TEMPERATURE
RANGE
LINEARITY
ERROR (%FSR)
MODEL
1–24
25–99
100+
ADC700JH
ADC700KH
ADC700AH
ADC700BH
ADC700RH
ADC700SH
0°C to 70°C
0°C to 70°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
±0.006
±0.003
±0.006
±0.003
±0.006
±0.003
®
3
ADC700
BB [ BURR-BROWN CORPORATION ]
