AZ100LVEL16VR
MLP 8, 2x2 mm Package (VRNE)
A CMOS enable input (EN) allows continuous oscillator operation. When the EN input is HIGH or left open
(NC), the Q¯ and QHG/Q¯HG outputs follow the data input. When EN is LOW, the QHG output is forced high and the Q¯
HG output is forced low while Q¯ continues to follow the data input. The Q¯ output has an internal 4 mA current source
to VEE, in most cases eliminating the need for an external pull-down resistor.
The data input D is tied to the VBB pin through a 470 Ω internal bias resistor while the inverting input D¯ is
connected directly to VBB. Bypassing VBB to ground with a 0.01 μF capacitor is recommended.
NOTE: The specifications in the ECL/PECL tables are valid when thermal equilibrium has been established.
PIN DESCRIPTION
4mA
PIN
FUNCTION
Data Input
Data Output
Data Outputs w/High Gain
Reference Voltage Output
Enable Input
Q
D
D
Q¯
QHG
QHG
QHG/Q¯HG
VBB
470
EN
VEE
VCC
VEE
VBB
EN
Negative Supply
Positive Supply
AZ100LVEL16VRNE
D
AZ100LVEL16VRNE
MLP 8, 2x2 mm
(CMOS Input
Levels)
EN
D
1
Q
8
Q
Leave Pad
VBB
VCC
QHG
QHG
7
6
5
2
3
open or
connect to
VEE
QHG
EN
VEE
4
QHG
TIMING DIAGRAM
TOP VIEW
April 2007 * REV - 15
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AZM [ ARIZONA MICROTEK, INC ]
