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AS5C1008DJ-25/XT 参数 Datasheet PDF下载

AS5C1008DJ-25/XT图片预览
型号: AS5C1008DJ-25/XT
PDF下载: 下载PDF文件 查看货源
内容描述: 128K ×8 SRAM耐用的塑料高速SRAM [128K x 8 SRAM RUGGEDIZED PLASTIC HIGH SPEED SRAM]
分类和应用: 内存集成电路静态存储器光电二极管
文件页数/大小: 9 页 / 102 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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SRAM  
AS5C1008  
Austin Semiconductor, Inc.  
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS  
(-55oC<TA<+125oC or -40oC to +85oC;Vcc = 5V+10%)  
-15  
-20  
-25  
PARAMETER  
CONDITIONS  
Vcc=MAX, IOUT = 0mA,  
SYMBOL MIN MAX MIN MAX MIN MAX UNITS  
Dynamic Operating  
Current  
ICC1  
180  
90  
150  
75  
140  
70  
mA  
mA  
CE1 = VIL and CE2 = VIH, f = fmax  
Vcc=MAX, VIN = VIH or VIL,  
TTL Standby Current -  
TTL Inputs  
ISB1  
CE\1> VIH and CE2 > VIL, f = fmax  
Vcc=MAX, CE\1 > Vcc -0.2V, or CE2  
< 0.2V, VIN > Vcc -0.2V and  
CMOS Standby Current -  
CMOS Inputs  
10  
10  
10  
mA  
ISB2  
VIN < 0.2V, f = 0  
Input Leakage Current  
Output Leakage Current  
-10  
-10  
2.4  
10  
10  
-10  
-10  
2.4  
10  
10  
-10  
-10  
2.4  
10  
10  
µA  
µA  
GND < VIN < Vcc  
ILI  
GND < VOUT < Vcc  
Output Disabled  
ILO  
Output High Voltage  
Output Low Voltage  
V
V
Vcc = MIN, IOH = -4.0 mA  
VOH  
VOL  
0.4  
0.4  
0.4  
Vcc = MIN, IOL = 8.0 mA  
Vcc  
+0.5  
Vcc  
+0.5  
Vcc  
+0.5  
Input High Voltage  
Input Low Voltage  
VIH  
VIL  
2.2  
2.2  
2.2  
V
V
-0.5 0.8 -0.5 0.8 -0.5 0.8  
PIN DESCRIPTIONS  
A0 - A16: Address Inputs  
OE\:OutputEnableInput  
The Output Enable Input is asserted LOW. If asserted LOW  
These 17 address inputs select one of the 131,072 8-bit words in  
the RAM.  
while CE\1 is asserted (LOW) and CE2 is asserted (HIGH) and  
WE\ is deasserted (HIGH), data from the SRAM will be present  
on the I/O pins. The I/O pins will be in the high-impedance  
state when OE\ is deasserted.  
CE\1: Chip Enable 1 Input  
CE\1 is asserted LOW to read from or write to the device. If Chip  
Enable 1 is deasserted, the device is deselected and is in standby  
power mode. The I/O pins will be in the high-impedance state  
when the device is deselected.  
WE\: Write Enable Input  
The Write Enable input is asserted LOW and controls read and  
write operations. When CE\1 and WE\ are both asserted (LOW)  
and CE2 is asserted (HIGH) input data present on the I/O pins  
will be written into the selected memory location.  
CE2: Chip Enable 2 Input  
CE2 is asserted HIGH to read from or write to the device. If Chip  
Enable 2 is deasserted, the device is deselected and is in standby  
power mode. The I/O pins will be in the high-impedance state  
when the device is deselected.  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS5C1008  
Rev. 3.5 1/01  
3