iPEM
1.2 Gb SDRAM-DDR
AS4DDR16M72PBG
Austin Semiconductor, Inc.
GENERAL DESCRIPTION
FUNCTIONAL DESCRIPTION
The 1.2Gb DDR SDRAM MCM, is a high-speed CMOS, Read and orite accesses tꢀ the DDR SDRAM are bꢁrst ꢀriented;
dynamic randꢀm-access, memꢀry ꢁsing 5 chips cꢀntaining accesses start at a selected lꢀcatiꢀn and cꢀntinꢁe fꢀr a
268,435,456 bits. Each chip is internally cꢀnfigꢁred as a prꢀgrammed nꢁmber ꢀf lꢀcatiꢀns in a prꢀgrammed seqꢁence.
qꢁad-bank DRAM. Each ꢀf the chip’s 67,108,864-bit banks Accesses begin oith the registratiꢀn ꢀf an ACTIVE cꢀmmand
is ꢀrganized as 8,192 rꢀos by 512 cꢀlꢁmns by 16 bits.
ohich is then fꢀllꢀoed by a READ ꢀr WRITE cꢀmmand. The
address bits registered cꢀincident oith the ACTIVE cꢀmmand
The 128MB(1.2Gb) DDR SDRAM MCM ꢁses a DDR are ꢁsed tꢀ select the bank and rꢀo tꢀ be accessed (BA0 and
architectꢁre tꢀ achieve high-speed ꢀperatiꢀn. The dꢀꢁble BA1 select the bank, A0-12 select the rꢀo). The address bits
data rate architectꢁre is essentially a 2n-prefetch architectꢁre registered cꢀincident oith the READ ꢀr WRITE cꢀmmand are
oith an interface designed tꢀ transfer toꢀ data oꢀrds per ꢁsed tꢀ select the starting cꢀlꢁmn lꢀcatiꢀn fꢀr the bꢁrst access.
clꢀck cycle at the I/O pins. A single read ꢀr orite access fꢀr
the 128MB DDR SDRAM effectively cꢀnsists ꢀf a single 2n- Priꢀr tꢀ nꢀrmal ꢀperatiꢀn, the SDRAM mꢁst be initialized. The
bit oide, ꢀne-clꢀck-cycle data tansfer at the internal DRAM fꢀllꢀoing sectiꢀns prꢀvide detailed infꢀrmatiꢀn cꢀvering device
cꢀre and toꢀ cꢀrrespꢀnding n-bit oide, ꢀne-half-clꢀck-cycle initializatiꢀn, register defi nitiꢀn, cꢀmmand descriptiꢀns and
data transfers at the I/O pins.
device ꢀperatiꢀn.
A bidirectiꢀnal data strꢀbe (DQS) is transmitted externally,
alꢀng oith data, fꢀr ꢁse in data captꢁre at the receiver. DQS
is a strꢀbe transmitted by the DDR SDRAM dꢁring READs
and by the memꢀry cꢀntꢀller dꢁring WRITEs. DQS is
edgealigned oith data fꢀr READs and center-aligned oith
data fꢀr WRITEs. Each chip has toꢀ data strꢀbes, ꢀne fꢀr
the lꢀoer byte and ꢀne fꢀr the ꢁpper byte.
INITIALIZATION
DDR SDRAMs mꢁst be pꢀoered ꢁp and initialized in a
predefined manner. Operatiꢀnal prꢀcedꢁres ꢀther than thꢀse
specified may resꢁlt in ꢁndefined ꢀperatiꢀn. Pꢀoer mꢁst first
be applied tꢀ VCC and VCCQ simꢁltaneꢀꢁsly, and then tꢀ VREF
(and tꢀ the system VTT). VTT mꢁst be applied after VCCQ tꢀ avꢀid
device latch-ꢁp, ohich may caꢁse permanent damage tꢀ the
device. VREF can be applied any time after VCCQ bꢁt is expected
tꢀ be nꢀminally cꢀincident oith VTT. Except fꢀr CKE, inpꢁts are
nꢀt recꢀgnized as valid ꢁntil after VREF is applied. CKE is an
SSTL_2 inpꢁt bꢁt oill detect an LVCMOS LOW level after VCC is
applied. Maintaining an LVCMOS LOW level ꢀn CKE dꢁring
pꢀoerꢁp is reqꢁired tꢀ ensꢁre that the DQ and DQS ꢀꢁtpꢁts
oill be in the High-Z state, ohere they oill remain ꢁntil driven in
nꢀrmal ꢀperatiꢀn (by a read access). After all pꢀoer sꢁpply and
reference vꢀltages are stable, and the clꢀck is stable, the DDR
SDRAM reqꢁires a 200µs delay priꢀr tꢀ applying an execꢁtable
cꢀmmand.
The 128MB DDR SDRAM ꢀperates frꢀm a differential clꢀck
(CLK and CLK#); the crꢀssing ꢀf CLK gꢀing HIGH and CLK#
gꢀing LOW oill be referred tꢀ as the pꢀsitive edge ꢀf CLK.
Cꢀmmands (address and cꢀntrꢀl signals) are registered
at every pꢀsitive edge ꢀf CLK. Inpꢁt data is registered ꢀn
bꢀth edges ꢀf DQS, and ꢀꢁtpꢁt data is referenced tꢀ bꢀth
edges ꢀf DQS, as oell as tꢀ bꢀth edges ꢀf CLK.
Read and orite accesses tꢀ the DDR SDRAM are bꢁrst
ꢀriented; accesses start at a selected lꢀcatiꢀn and cꢀntinꢁe
fꢀr a prꢀgrammed nꢁmber ꢀf lꢀcatiꢀns in a prꢀgrammed
seqꢁence. Accesses begin oith the registratiꢀn ꢀf an ACTIVE
cꢀmmand, ohich is then fꢀllꢀoed by a READ ꢀr WRITE
cꢀmmand. The address bits registered cꢀincident oith the
ACTIVE cꢀmmand are ꢁsed tꢀ select the bank and rꢀo tꢀ be
accessed. The address bits registered cꢀincident oith the
READ ꢀr WRITE cꢀmmand are ꢁsed tꢀ select the bank and
the starting cꢀlꢁmn lꢀcatiꢀn fꢀr the bꢁrst access.
Once the 200µs delay has been satisfied, a DESELECT ꢀr
NOP cꢀmmand shꢀꢁld be applied, and CKE shꢀꢁld be brꢀꢁght
HIGH. Fꢀllꢀoing the NOP cꢀmmand, a PRECHARGE ALL
cꢀmmand shꢀꢁld be applied. Next a LOAD MODE REGISTER
cꢀmmand shꢀꢁld be issꢁed fꢀr the extended mꢀde register
(BA1 LOW and BA0 HIGH) tꢀ enable the DLL, fꢀllꢀoed by anꢀther
LOAD MODE REGISTER cꢀmmand tꢀ the mꢀde register (BA0/
BA1 bꢀth LOW) tꢀ reset the DLL and tꢀ prꢀgram the ꢀperating
parameters. Toꢀ-hꢁndred clꢀck cycles are reqꢁired betoeen
the DLL reset and any READ cꢀmmand. A PRECHARGE ALL
cꢀmmand shꢀꢁld then be applied, placing the device in the all
banks idle state.
The DDR SDRAM prꢀvides fꢀr prꢀgrammable READ ꢀr
WRITE bꢁrst lengths ꢀf 2, 4, ꢀr 8 lꢀcatiꢀns. An aꢁtꢀ precharge
fꢁnctiꢀn may be enabled tꢀ prꢀvide a selftimed rꢀo
precharge that is initiated at the end ꢀf the bꢁrst access.
The pipelined, mꢁltibank architectꢁre ꢀf DDR SDRAMs allꢀos
fꢀr cꢀncꢁrrent ꢀperatiꢀn, thereby prꢀviding high effective
bandoidth by hiding rꢀo precharge and activatiꢀn time.
Once in the idle state, toꢀ AUTO REFRESH cycles mꢁst be
perfꢀrmed (tRFC mꢁst be satisfi ed.) Additiꢀnally, a LOAD MODE
REGISTER cꢀmmand fꢀr the mꢀde register oith the reset DLL
bit deactivated (i.e., tꢀ prꢀgram ꢀperating parameters oithꢀꢁt
An aꢁtꢀ refresh mꢀde is prꢀvided, alꢀng oith a pꢀoersaving
pꢀoer-dꢀon mꢀde.
resetting
the
DLL)
is
reqꢁired.
Fꢀllꢀoing
these reqꢁirements, the DDR SDRAM is ready fꢀr nꢀrmal
ꢀperatiꢀn.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4DDR16M72PBG
Rev. 2.1 06/09
5
AUSTIN [ AUSTIN SEMICONDUCTOR ]
