FLASH
AS29F040
Austin Semiconductor, Inc.
power-down. The command register and all internal program/ The device is also ready to read array data after completing an
erase circuits are disabled, and the device resets. Subsequent Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the
device enters the Erase Suspend mode. The system can read
array data using the standard read timings, except that if it
reads at an address within erase-suspended sectors, the device
outputs status data. After completing a programming
operation in the Erase Suspend mode, the system may once
again read array data with the same exception. See “Erase
Suspend/Erase Resume” for more information.
writes are ignored until VCC is greater than VLKO. The system
must provide the proper signals to the control pins to prevent
unintentional writes when VCC is greater than VLKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5ns (typical) on OE\, CE\, or WE\
do not initiate a write cycle.
The system must issue the reset command to re-enable the
device for reading array data if DQ5 goes high, or while in the
autoselect mode. See the “Reset Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information. The
Read Operations table provides the read parameters, and the
Read Operation Timings diagram shows the timing diagram.
Logical Inhibit
Write cycles are inhibited by holding any one of OE\ = VIL,
CE\ = VIH or WE\ = VIH. To initiate a write cycle, CE\ and WE\
must be a logical zero while OE\ is a logical one.
Power-Up Write Inhibit
If WE\ = CE\ = VIL and OE\ = VIH during power up, the
device does not accept commands on the rising edge of WE\.
The internal state machine is automatically reset to reading
array data on power-up.
Reset Command
Writing the reset command to the device resets the device
to reading array data. Address bits are don’t care for this
command.
The reset command may be written between the sequence
cycles in an erase command sequence before erasing begins.
COMMAND DEFINITIONS
Writing specific address and data commands or sequences This resets the device to reading array data. Once erasure
into the command register initiates device operations. The begins, however, the device ignores reset commands until the
Command Definitions table defines the valid register command operation is complete.
sequences. Writing incorrect address and data values or
writing them in the improper sequence resets the device to cycles in a program command sequence before programming
reading array data. begins. This resets the device to reading array data (also applies
The reset command may be written between the sequence
All addresses are latched on the falling edge of WE\ or to programming in Erase Suspend Mode). Once programming
CE\, whichever happens later. All data is latched on the rising begins, however, the device ignores reset commands until the
edge of WE\ or CE\, whichever happens first. Refer to the operation is complete.
appropriate timing diagrams in the “AC Characteristics”
section.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve data.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to return
to reading array data (also applies to autoselect during Erase
Suspend).
TABLE 3: Autoselect Codes (High Voltage Method)
Identifier Code
On DQ7 to DQ0
Description
A18 - A16 A15 - A10 A9
A8 - A7
A6
A5 - A2
A1
A0
Manufacturer ID
Device ID
X
X
X
X
V
V
X
X
V
V
X
X
V
V
V
01h
ID
IL
IL
IL
V
A4h
ID
IL
IL
IH
01h (protected)
Sector Protection
Verification
Sector
Address
X
V
X
V
X
V
V
IL
ID
IL
IH
00h
(unprotected)
AS29F040
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 2.2 09/07
6
AUSTIN [ AUSTIN SEMICONDUCTOR ]
