FLASH
AS29F040
Austin Semiconductor, Inc.
GENERAL DESCRIPTION
The AS29F040 is a 4Mbit, 5.0 Volt-only FLASH memory program pulse widths and verifies proper cell margin.
organized as 524,288 Kbytes of 8 bits each. The 512 Kbytes of
Device erasure occurs by executing the erase command
data are divided into eight sectors of 64 Kbytes each for flexible sequence. This invokes the Embedded Erase algorithm -- an
erase capability. The 8 bits of data appear on DQ0-DQ7. The internal algorithm that automatically preprograms the array (if it
device is designed to be programmed in-system with the is not already programmed) before executing the erase
operation. During erase, the device automatically times the
erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase
operation is complete by reading the DQ7 (Data\Polling) and
DQ6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or accept
another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data contents
of other sectors. The device is fully erased when shipped from
the factory.
standard system 5.0 Volt VCC supply. A 12.0 volt VPP is not
required for write or erase operations. The device can also be
programmed in standard EPROM programmers.
This device is manufactured using 0.32 µm process
technology. In addition, it has a second toggle bit, DQ2, and
offers the ability to program in the Erase Suspend mode.
It is available with access times of 55, 60, ^+^+6=70, 90, 120,
and 150ns, allowing high-speed microprocessors to operate with-
out wait states. To eliminate bus contention the device has
separate chip enable (CE\), write enable (WE\), and output en-
able (OE\) controls.
The hardware data protection measures include a low VCC
The device requires only a single 5.0 volt power supply for
both read and write functions. Internally generated and detector that automatically inhibits write operations during
regulated voltages are provided for the program and erase power transitions. The hardware sector protection feature
operations.
disables both program and erase operations in any
The device is entirely command set compatible with the combination of the sectors of memory. This can be achieved
JEDEC single-power-supply FLASH standard. Commands are via programming equipment.
written to the command register using standard microprocessor
The erase suspect feature enables the user to put erase on
write timings. Register contents serve as input to an internal hold for any period of time to read data from, or program data to,
state-machine that controls the erase and programming circuitry. any sector that is not selected for erasure. True background
Write cycles also internally latch addresses and data needed for erase can thus be achieved.
the programming and erase operations. Reading data out of the
device is similar to reading from other FLASH or EPROM Power consumption is greatly reduced in this mode. The
devices.
device electrically erases all bits within a sector simultaneously
The system can place the device into the standby mode.
Device programming occurs by executing the program via Fowler-Nordheim tunneling. The data is programmed using
command sequence. This invokes the Embedded Program hot electron injection.
algorithm -- an internal algorithm that automatically times the
PIN CONFIGURATION
LOGIC SYMBOL
PIN
DESCRIPTION
A0 - A18 Address Inputs
DQ0 - DQ7 Data Inputs/Outputs
CE\
OE\
WE\
Chip Enable
Output Enable
Write Enable
V
+5V Single Power Supply
Device Ground
CC
V
SS
AS29F040
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 2.2 09/07
2
AUSTIN [ AUSTIN SEMICONDUCTOR ]
