AWT6222
APPLICATION INFORMATION
The Bias Control table lists the recommended modes
of operation for various applications. VMODE2 is not
necessary for this PA.
To ensure proper performance, refer to all related
Application Notes on the ANADIGICS web site:
http://www.anadigics.com
Two operating modes are available to optimize current
consumption. High Bias/High Power operating mode
is for POUT levels > 16 dBm. At around 16 dBm output
power, the PAshould be “Mode Switched” to Low power
mode for lowest quiescent current consumption.
Shutdown Mode
The power amplifier may be placed in a shutdown
mode by applying logic low levels (see Operating
Ranges table) to the VENABLE and VMODE1 pins.
Bias Modes
The power amplifier may be placed in either a Low Bias
mode or a High Bias mode by applying the appropriate
logic level (see Operating Ranges table) to VMODE1.
Table 6: Bias Control
P
OUT
BIAS
MODE
APPLICATION
V
ENABLE
V
MODE1
V
CC
V
BATT
LEVELS
< +16 dBm
> +16 dBm
< +7 dBm
-
UMTS - low power
UMTS - high power
OPTIONAL - low power
Shutdown
Low
High
+2.4 V +2.4 V
+2.4 V 0 V
+2.4 V +2.4 V
0 V 0 V
3.2 - 4.2 V
3.2 - 4.2 V
1.5 - 3.2 V
3.2 - 4.2 V
> 3.2 V
> 3.2 V
> 3.2 V
> 3.2 V
Low
Shutdown
GND at slug (pad)
V
EN_CELL
1
14
13
12
11
10
9
GND
0.01 F
Bias Control
(1)
RFIN_CELL
(3)
(3)
68 pF
TRL1
2
TRL2
RFOUT_CELL
VMODE
VCC
3
1000 pF
(4)
V
BATT
TRL5
4
(2)
68 pF
2.2 F
2.2 F
5
GND
GND
N/C
(1)
(3)
RFIN_IMT
TRL3
6
7
Bias Control
(3)
68 pF
TRL4
RFOUT_IMT
VEN_IMT
8
0.01 F
GND
Note:
(1) Add blocking cap if DC voltage is present on input pin.
(2) 68 pF cap should be placed as close as possible to Pin 4.
(3) TRL should be short and of 50 characteristic impedance.
(4) TRL 5 should be as long as possible (minimum of 0.1 at 800 MHz) and capable of handling 750 mA current.
Optional 4.7 nH Inductor may be substituted.
Figure 3: Application Circuit
Data Sheet - Rev 2.1
11/2008
6
ANADIGICS [ ANADIGICS, INC ]
