SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
Receiver
S3005/S3006 OVERVIEW
1. Clock and data recovery from serial input
2. CMI decoding (optional)
3. Frame detection
4. Serial-to-parallel conversion
5. 8-bit parallel output
The S3005 SETI and S3006 SERI implement
SONET/SDH serialization/deserialization, transmission,
and frame detection/recovery functions. The block
diagrams in Figures 4 and 5 show basic operation of
both chips. These chips can be used to implement the
front end of SONET equipment, which consists primarily
of the serial transmit interface (S3005) and the serial
receive interface (S3006). The chipset handles all
the functions of these two elements, including paral-
lel-to-serial and serial-to-parallel conversion, clock
generation and recovery, and system timing, which
includes management of the datastream, framing, and
clock distribution throughout the front end.
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figures 10 through 18. On-chip clock generation can
be bypassed and an externally generated clock used
in its place, providing an additional measure of
design flexibility.
A lock detect feature is provided on both chips.
Suggested Interface Devices
Operation of the S3005/S3006 chips is straightfor-
ward. The sequence of operations is as follows:
PMC PM5345
PMC PM5355
IGT WAC–013–A
SUNI
Saturn User Network Interface
Saturn User Network Interface
SONET LAN ATM Processor
Network Termination Controller
Section Terminating Transceiver
Transport Terminating Transceiver
SUNI-622
Transmitter
1. 8-bit parallel input
Fujitsu MB86683B NTC
2. Parallel-to-serial conversion
3. CMI encoding (optional)
4. Serial output
PMC PM5301
PMC PM5312
SSTX
STTX
AT&T ASTROTEC1227/1230
Mitsubishi MF-622DF-T12-XXX 622 Mbit/s
AT&T ASTROTEC 1310 650 Mbit/s
Mitsubishi MF-622DS-R1X-XXX 622 Mbit/s
650 Mbit/s
Fiber Optic Transmitter
Fiber Optic Transmitter
Fiber Optic Receiver
Fiber Optic Receiver
Figure 4. SONET/SDH Transmitter Functional Block Diagram
DLEB
LLEB
2
LLDP/N
2
DLDP/N
LLCLKP/N
2
2
8
D
TSDP/N
PIN[7:0]
8:1 PARALLEL
TO SERIAL
CMI
PICLK
DLCV
LOAD
TSCLKP/N
PCLK
PAE
TIMING
GEN
SYNC
BYTCLKIP
TESTEN
CLOCK
SYNTHESIZER
3
2
2
MODE[2:0]
REFSEL[1:0]
REFCLKP/N
RSTB
LOCKDET
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
3
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
