SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
Line Loopback
The CMI decoder block on the S3006 SERI accepts
serial data from the RSDP/N input at the TSCLK rate
(311.04 MHz or 278.528 MHz). The data is then de-
coded from CMI to NRZ format and converted from
serial to parallel at one half the TSCLK rate.
The Line Loopback circuitry consists of alternate
clock and data output drivers. For the S3005, it selects
the source of the data and clock which is output on TSD
and TSCLK. When the Line Loopback Enable input
(LLEB) is high, it selects data and clock from the Parallel
to Serial Converter block or the CMI Encoder block.
When LLEB is low, it forces the output data multiplexor
to select data and clock from the LLD and LLCLK
inputs. When these inputs are connected to the Line
Loop Clock (LLCLK) and Line Loop Data (LLD) out-
puts of a S3006 receiver, a receive-to-transmit
loopback can be established at the serial data rate.
Note that in CMI operating mode, the data bit rate is
one half of the recovered clock rate.
Diagnostic Loopback
The Diagnostic Loopback path consists of alternate
serial data outputs (in the case of the S3005) and
inputs (in the case of the S3006).
On the S3005, the differential ECL output DLD pro-
vides Diagnostic Loopback serial data. When the
Diagnostic Loopback Enable (DLEB) input is low,
this data output is a replica of TSD. When DLD is
connected to the S3006, a loopback from the trans-
mitter to the receiver at the serial data rate can be
set up for diagnostic purposes. When DLEB is high,
DLD is held in the inactive state, with the positive
output high and the negative output low. In the inac-
tive state, there will be no interference from the
transmitter to the receiver. The DLD outputs on the
S3005 should be held inactive (DLEB high) when not
in use to avoid potential crosstalk of the asynchro-
nous DLD signals with the serial data signals.
Test and Bypass Modes
The Test Clock Enable (TESTEN) inputs on both
chips provide access to the PLL.
The PLL-generated clock source on both the S3005
and S3006 can be bypassed by setting TESTEN
high. In this mode, an externally generated bit serial
clock source must be applied at the REFCLK input.
Table 6 lists the possible combinations allowed in
bypass mode.
On the receiver side, the differential ECL input DLD
is the Diagnostic Loopback serial data input. When
the Diagnostic Loopback Enable (DLEB) input is set
low, the DLD input is routed in place of the normal
data stream (RSD).
Table 6. Bypass Mode
TESTEN
MODE[2:0]
Reference Clock Frequency
Serial Data Rate
(Mbit/s)
In Bypass Mode
0
XXX
Normal Operating Mode
(See Table 2)
—
1
1
1
1
100
101
101
110
622.08
311.04
278.528
155.52
622.08
155.52 CMI
139.264 CMI
155.52
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