2–2
Chapter 2: Arria GX Architecture
Transceivers
Figure 2–1 shows a high-level diagram of the transceiver block architecture divided
into four channels.
Figure 2–1. Transceiver Block
Transceiver Block
RX1
Channel 1
TX1
RX0
Channel 0
Arria GX
Logic Array
TX0
Supporting Blocks
(PLLs, State Machines,
Programming)
REFCLK_1
REFCLK_0
RX2
Channel 2
Channel 3
TX2
RX3
TX3
Each transceiver block has:
■
■
■
■
Four transceiver channels with dedicated physical coding sublayer (PCS) and
physical media attachment (PMA) circuitry
One transmitter PLL that takes in a reference clock and generates high-speed serial
clock depending on the functional mode
Four receiver PLLs and clock recovery unit (CRU) to recover clock and data from
the received serial data stream
State machines and other logic to implement special features required to support
each protocol
Figure 2–2 shows functional blocks that make up a transceiver channel.
Figure 2–2. Arria GX Transceiver Channel Block Diagram
PMA Analog Section
PCS Digital Section
FPGA Fabric
n
Word
Deserializer
Aligner
(1)
m
Phase
Compensation
FIFO Buffer
Rate
Matcher
8B/10B
Decoder
Byte
Deserializer
Clock
Recovery
Unit
(2)
XAUI
Lane
Deskew
Reference
Clock
Receiver
PLL
Transmitter
PLL
Reference
Clock
n
Serializer
m
Phase
Compensation
FIFO Buffer
Byte
Serializer
(1)
8B/10B
Encoder
(2)
Notes to Figure 2–2:
(1) “n” represents the number of bits in each word that must be serialized by the transmitter portion of the PMA.
n = 8 or 10.
(2) “m” represents the number of bits in the word that passes between the FPGA logic and the PCS portion of the transceiver. m = 8, 10, 16, or 20.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
