Chapter 1: Arria GX Device Family Overview
1–3
Features
Table 1–1. Arria GX Device Features (Part 2 of 2)
EP1AGX20C
C
EP1AGX35C/D
EP1AGX50C/D
EP1AGX60C/D/E
D
EP1AGX90E
E
Feature
Source-
C
D
C
D
C
E
synchronous
transmit
29
29
29
29
29, 42
29
29
42
45
channels
M512 RAM
blocks
(32 × 18 bits)
166
118
197
140
313
242
326
252
478
400
M4K RAM
blocks
(128 × 36
bits)
M-RAM
blocks
(4096 × 144
bits)
1
1
2
2
4
Total RAM
bits
1,229,184
40
1,348,416
56
2,475,072
2,528,640
128
4,477,824
176
Embedded
multipliers
(18 × 18)
104
26
DSP blocks
PLLs
10
4
14
4
32
4
44
8
4
4, 8
8
Maximum
user I/O pins
230, 341
230
341
229
350, 514
229
350
514
538
Arria GX devices are available in space-saving FBGA packages (refer to Table 1–2). All
Arria GX devices support vertical migration within the same package. With vertical
migration support, designers can migrate to devices whose dedicated pins,
configuration pins, and power pins are the same for a given package across device
densities. For I/O pin migration across densities, the designer must cross-reference
the available I/O pins with the device pin-outs for all planned densities of a given
package type to identify which I/O pins are migratable.
Table 1–2. Arria GX Package Options (Pin Counts and Transceiver Channels) (Part 1 of 2)
Source-Synchronous Channels Maximum User I/O Pin Count
Transceiver
Channels
1152-Pin
FBGA
(35 mm)
Device
484-Pin FBGA
(23 mm)
780-Pin FBGA
(29 mm)
Receive
Transmit
EP1AGX20C
EP1AGX35C
EP1AGX50C
EP1AGX60C
EP1AGX35D
EP1AGX50D
4
4
4
4
8
8
31
31
29
29
230
230
229
229
—
341
—
—
—
31
29
—
—
31
29
—
—
31
29
341
350
—
31, 42
29, 42
—
514
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
