Preliminary
January 2006
Typical Output
Ripple (mV)
Over-Current Protection
Output Capacitor Configuration
1 x 47uF
3 x 22 uF
5 x 10 uF
tbd
tbd
tbd
The current limit function is achieved by sensing the
current flowing through the sense P-MOSFET. When
the sensed current exceeds the current limit, both
NFET and PFET switches are turned off for 4 clock
cycles. If the over-current condition is removed, the
over-current protection circuit will enable the PWM
operation. If the over-current condition persists, the
soft start capacitor will eventually discharge and cause
the converter to go through a full soft-start cycle. This
circuit is designed to provide high noise immunity.
Enable Operation
The ENABLE pin provides a means to shut down the
device, or enable normal operation. A logic low will
disable the converter and cause it to shut down. A
logic high will enable the converter into normal
operation. When the ENABLE pin is asserted high,
the device will undergo a normal soft start.
It is possible to adjust the over-current set point by
connecting a resistor between ROCP (pin 38) and
GND (increase the trip point) or PVIN (decrease the
trip point). The nominal over current trip point is set
to 9A. The voltage at the ROCP pin is designed to be
0.8V.
Soft-Start Operation
Soft start is a method to reduce in-rush current when
the device is enabled. The output voltage is ramped up
slowly upon start-up.
The output rise time is
controlled by choice of a soft-start capacitor, which is
placed between the SS pin (pin 48) and the AGND pin
(pin 40).
In some cases, such as the start-up of FPGA devices,
it is desirable to blank the over-current protection
feature. In order to disable over-current protection, the
ROCP pin should be tied to PVIN.
Rise Time: TR = Css* 80KΩ
Over-Voltage Protection
During start-up of the converter, the reference voltage
to the error amplifier is gradually increased to its final
level by an internal current source of typically 10uA.
Typical soft-start rise time is 1mS to 3mS. Typical SS
capacitor values are in the range of 15nF to 30 nF.
When the output voltage exceeds 120% of the
programmed output voltage, the PWM operation
stops, the lower N-MOSFET is turned on and the
POK signal goes low. When the output voltage drops
below 95% of the programmed output voltage, normal
PWM operation resumes and POK returns to its high
state.
POK Operation
The POK signal is an open drain signal from the
converter indicating the output voltage is within the
specified range. The POK signal will be a logic high
when the output voltage is within 90% - 120% of the
programmed output voltage. If the output voltage goes
outside of this range, the POK signal will be a logic
low until the output voltage has returned to within this
range. In the event of an over-voltage condition the
POK signal will go low and will remain in this
condition until the output voltage has dropped to 95%
of the programmed output voltage before returning to
the high state (see also: Over Voltage Protection)
Thermal Overload Protection
Thermal shutdown will disable operation once the
Junction temperature exceeds approximately 160ºC.
Once the junction temperature drops by approx 25ºC,
the converter will re-start with a normal soft-start.
Input Under-voltage Lock-out
Circuitry is provided to ensure that when the input
voltage is below the specified voltage range, the
converter will not start-up. Circuits for hysteresis,
input de-glitch and output leading edge blanking are
www.enpirion.com
7
ALTERA [ ALTERA CORPORATION ]
