Preliminary
January 2006
PIN
NAME
FUNCTION
NO CONNECT – Do not electrically connect these pins to each other or to PCB.
CAUTION!: Internally connected to switching node. Take care to route signals away
from these pins.
21-23
NC
Output power ground. Connect these pins to the ground electrode of the output filter
capacitors. Refer to layout guideline section.
Input power ground. Connect these pins to the ground electrode of the Input filter
capacitors. Refer to layout guideline section
Input power supply. Connect to input power supply. Decouple with input capacitor to
PGND (pins 24-29).
NO CONNECT – Do not electrically connect these pins to each other or to PCB.
CAUTION! May be internally connected.
24-27
28-29
30-35
36-37
38
PGND
PGND
PVIN
NC
Optional Over Current Protection adjust pin. Place ROCP resistor between this pin and
AGND (pin 40) to adjust the over current trip point.
ROCP
Analog voltage input for the controller circuits. Connect this pin to the input power
supply.
Analog ground for the controller circuits.
NO CONNECT – Do not electrically connect these pins to each other or to PCB.
CAUTION! May be internally connected.
39
40
AVIN
AGND
NC
41-42
43
44
45
VS2
VS1
VS0
Voltage select line 2 input. See Table 1.
Voltage select line 1 input. See Table 1.
Voltage select line 0 input. See Table 1.
Power OK is an open drain transistor for power system state indication. POK is a
logic high when VOUT is with -10% to +20% of VOUT nominal.
Remote voltage sense input. Connect this pin to the load voltage at the point to be
regulated.
Soft-Start node. The soft-start capacitor is connected between this pin and AGND.
The value of this resistor determines the startup timing.
46
47
48
POK
VSENSE
SS
49
50
51
EAIN
EAOUT
COMP
Optional Error Amplifier input. Allows for customization of the control loop.
Optional Error Amplifier output. Allows for customization of the control loop.
Optional Error Amplifier Buffer output. Allows for customization of the control loop.
Input Enable. Applying a logic high, enables the output and initiates a soft-start.
Applying a logic low disables the output.
PWM input/output. Used for optional master/slave configuration. When M/S pin is
asserted “low”, PWM will output the gate-drive PWM waveform. When the M/S pin
is asserted “high”, the PWM pin is configured as an input for PWM signal from the
“master” device. PWM pin can drive up to 3 slave devices.
NO CONNECT – Do not electrically connect these pins to each other or to PCB.
CAUTION! May be internally connected.
52
ENABLE
PWM
NC
53
54
Optional Master/Slave select pin. Asserting pin “low” places device in Master Mode
for current sharing. PWM pin (53) will output PWM drive signal. Asserting pin
“high” will place the device in Slave Mode. PWM pin (53) will be configured to input
(receive) PWM drive signal from “Master” device.
55
M/S
NO CONNECT – Do not electrically connect these pins to each other or to PCB.
CAUTION! May be internally connected.
56-58
NC
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