Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Programming/Erasure Specifications
Table 9.
Programming/Erasure Specifications for Intel MAX 10 Devices
This table shows the programming cycles and data retention duration of the user flash memory (UFM) and configuration flash memory (CFM) blocks.
For more information about data retention duration with 10,000 programming cycles for automotive temperature devices, contact your Intel quality
representative.
Erase and reprogram cycles (E/P) (8) (Cycles/
Temperature (°C)
Data retention duration (Years)
page)
10,000
10,000
85
20
10
100
DC Characteristics
Supply Current and Power Consumption
Intel offers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Intel Quartus
Prime Power Analyzer feature.
Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a
magnitude estimate of the device power because these currents vary greatly with the usage of the resources.
The Intel Quartus Prime Power Analyzer provides better quality estimates based on the specifics of the design after you
complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated
signal activities that, when combined with detailed circuit models, yield very accurate power estimates.
Related Links
•
Early Power Estimator User Guide
Provides more information about power estimation tools.
•
Power Analysis chapter, Intel Quartus Prime Handbook
Provides more information about power estimation tools.
(8)
The number of E/P cycles applies to the smallest possible flash block that can be erased or programmed in each Intel MAX 10 device.
Each Intel MAX 10 device has multiple flash pages per device.
Intel® MAX® 10 FPGA Device Datasheet
9
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