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10M02SCU169C8G 参数 Datasheet PDF下载

10M02SCU169C8G图片预览
型号: 10M02SCU169C8G
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, PBGA169, 11 X 11 MM, 0.80 MM PITCH, ROHS COMPLIANT, UBGA-169]
分类和应用: 时钟可编程逻辑
文件页数/大小: 71 页 / 822 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Intel® MAX® 10 FPGA Device Datasheet  
M10-DATASHEET | 2017.12.15  
Symbol  
Parameter  
Condition  
1.35 V  
1.2 V  
Min  
1.2825  
1.14  
Typ  
1.35  
Max  
1.4175  
1.26  
Unit  
V
1.2  
V
(1)  
VCCA  
Supply voltage for PLL regulator and ADC block  
(analog)  
2.85/3.135  
3.0/3.3  
3.15/3.465  
V
Dual Supply Devices Power Supplies Recommended Operating Conditions  
Table 7.  
Power Supplies Recommended Operating Conditions for Intel MAX 10 Dual Supply Devices  
Symbol  
Parameter  
Condition  
Min  
1.15  
Typ  
1.2  
3.3  
3
Max  
1.25  
Unit  
V
VCC  
Supply voltage for core and periphery  
Supply voltage for input and output buffers  
(3)  
VCCIO  
3.3 V  
3.0 V  
2.5 V  
1.8 V  
1.5 V  
1.35 V  
1.2 V  
3.135  
2.85  
3.465  
3.15  
V
V
2.375  
1.71  
2.5  
1.8  
1.5  
1.35  
1.2  
2.5  
1.2  
2.5  
1.2  
2.625  
1.89  
V
V
1.425  
1.2825  
1.14  
1.575  
1.4175  
1.26  
V
V
V
(4)  
VCCA  
Supply voltage for PLL regulator (analog)  
Supply voltage for PLL regulator (digital)  
Supply voltage for ADC analog block  
Supply voltage for ADC digital block  
2.375  
1.15  
2.625  
1.25  
V
(5)  
VCCD_PLL  
V
VCCA_ADC  
VCCINT  
2.375  
1.15  
2.625  
1.25  
V
V
(3)  
(4)  
VCCIO for all I/O banks must be powered up during user mode because VCCIO I/O banks are used for the ADC and I/O functionalities.  
All VCCA pins must be powered to 2.5 V (even when PLLs are not used), and must be powered up and powered down at the same  
time.  
(5)  
VCCD_PLL must always be connected to VCC through a decoupling capacitor and ferrite bead.  
Intel® MAX® 10 FPGA Device Datasheet  
7