AS4LC2M8S1
AS4LC1M16S1
®
AC parameters common to all waveforms
–7
–8
–10
CAS
Sym
Parameter
latency Min
Max
5.5
8.5
18
1
Min
–
Max
6
Min
–
Max
6
Unit
ns
Notes
6
3
2
1
–
–
–
–
2
0
tAC CLK to valid output delay
–
7
–
6
ns
6,8
6,8
7
–
22
1
–
22
1
ns
tAH Address hold time
tAS Address setup time
tBDL Last data-in to burst stop
–
–
ns
–
2
–
2
–
ns
7
–
0
–
0
–
tCK
9
Read/write command to
tCCD
1
1
–
–
1
1
–
–
1
1
–
–
tCK
tCK
9
9
read/write command
Last data-in to new
tCDL
column address delay
tCH CLK high-level width
2.75
7
–
3
8
–
3
–
ns
ns
ns
ns
7
3
2
1
1000
1000
1000
1000
1000
1000
10
12
25
1000
1000
1000
10
10
10
tCK CLK cycle time
8.7
20
10
25
CKE to CLOCK disable or
tCKED
1
–
1
–
1
–
tCK
power-down entry mode
tCKH CKE hold time
tCKS CKE setup time
tCL CLK low-level width
1
2
–
–
–
1
2
3
–
–
–
1
2
–
–
–
ns
ns
ns
2.75
3.5
7
CS, RAS, CAS, WE, DQM
hold time
tCMH
1
2
–
–
1
2
–
–
1
2
–
–
ns
ns
CS, RAS, CAS, WE, DQM
setup time
tCMS
3
2
1
5
5
4
1
2
1
–
–
–
–
–
–
5
5
4
1
2
1
–
–
–
–
–
–
5
5
4
1
2
1
–
–
–
–
–
–
tCK
tCK
tCK
ns
5,11
5,11
5,11
Data-in to ACTIVE
command
tDAL
tDH Data in hold time
tDPL Data in to PRECHARGE
tDQD DQM to input data delay
tCK
tCK
12
9
DQM to data mask during
writes
tDQM
0
–
0
–
0
–
tCK
9
9
DQM to data high Z
tDQZ
2
2
0
–
–
–
2
2
0
–
–
–
2
2
0
–
–
–
tCK
ns
during reads
tDS Data in setup time
Write command to input
data delay
tDWD
tCK
9
3
2
1
–
–
–
5.5
8.5
18
–
–
–
6
9
–
–
–
9
9
ns
ns
ns
13
13
13
Data-out high-impedance
time
tHZ
22
22
Data-out low-impedance
time
tLZ
1
–
1
–
1
–
ns
5/21/01; v.1.1
Alliance Semiconductor
P. 8 of 29
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
