A24C1024
TWO-WIRE SERIAL EEPROM
1024K (131.072 X 8)
AiT Semiconductor Inc.
www.ait-ic.com
address that is to be written into the address pointer of the A24C1024. After receiving another ACK from the
Slave, the Master device transmits the data byte to be written into the address memory location. The
A24C1024 acknowledges once more and the Master generates the Stop condition, at which time the device
begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to
any request from the Master device.
Page Write
The A24C1024 is capable of 256-byte Page-Write operation. A Page-Write is initiated in the same manner as
a Byte Write, but instead of terminating the internal Write cycle after the first data byte is transferred, the
Master device can transmit up to 255 more bytes. After the receipt of each data byte, the EEPROM responds
immediately with an ACK on SDA line, and the eight lower order data byte address bits are internally
incremented by one, while the higher order bits of the data byte address remain constant. If a byte address is
incremented from the last byte of a page, it returns to the first byte of that page. If the Master device should
transmit more than 256 bytes prior to issuing the Stop condition, the address counter will “roll over,” and the
previously written data will be overwritten. Once all 256 bytes are received and the Stop condition has been
sent by the Master, the internal programming cycle begins. At this point, all received data is written to the
A24C1024 in a single Write cycle. All inputs are disabled until completion of the internal Write cycle.
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage of the typical Write cycle time. Once the Stop
condition is issued to indicate the end of the host's Write operation, the A24C1024 initiates the internal Write
cycle. ACK polling can be initiated immediately. This involves issuing the Start condition followed by the Slave
address for a Write operation. If the EEPROM is still busy with the Write operation, no ACK will be returned. If
the A24C1024 has completed the Write operation, an ACK will be returned and the host can then proceed
with the next Read or Write operation.
Read Operation
Read operations are initiated in the same manner as Write operations, except that the (R/W) bit of the Slave
address is set to “1”. There are three Read operation options: current address read, random address read and
sequential read.
Current Address Read
The A24C1024 contains an internal address counter which maintains the address of the last byte accessed,
incremented by one. For example, if the previous operation is either a Read or Write operation addressed to
the address location n, the internal address counter would increment to address location n+1. When the
REV1.0
- JUN 2014 RELEASED -
- 9 -
AITSEMI [ AiT Semiconductor ]
