A24C1024
TWO-WIRE SERIAL EEPROM
1024K (131.072 X 8)
AiT Semiconductor Inc.
www.ait-ic.com
Reset
The A24C1024 contains a reset function in case the 2-wire bus transmission on is accidentally interrupted
(e.g. a power loss), or needs to be terminated mid-stream. The reset is initiated when the Master device
creates a Start condition. To do this, it may be necessary for the Master device to monitor the SDA line while
cycling the SCL up to nine times. (For each clock signal transition to High, the Master checks for a High level
on SDA.)
Standby Mode
While in standby mode, the power consumption is minimal. The A24C1024 enters into standby mode during
one of the following conditions: a) After Power-up, while no Op-code is sent; b) After the completion of an
operation and followed by the Stop signal, provided that the previous operation is not Write related; or c) After
the completion of any internal write operations.
Device Addressing
The Master begins a transmission on by sending a Start condition then sends the address of the particular
Slave devices to be communicated. The Slave device address is 8 bits format as shown in Figure.1-5.
The four most significant bits of the Slave address are fixed (1010) for A24C1024.
The next two bits, A1 and A2, of the Slave address are specifically related to EEPROM. Up to four A24C1024
units can be connected to the 2-wire bus.
The seventh bit is the memory page address A [16].
The last bit of the Slave address specifies whether a Read or Write operation is to be performed. When this bit
is set to 1, Read operation is selected. While it is set to 0, Write operation is selected.
After the Master transmits the Start condition and Slave address byte appropriately, the associated 2-wire
Slave device, A24C1024, will respond with ACK on the SDA line. Then A24C1024 will pull down the SDA on
the ninth clock cycle, signaling that it received the eight bits of data.
The A24C1024 then prepares for a Read or Write operation by monitoring the bus.
Write Operation
Access each data in the memory requires a 17-bit address. (The Most significant bit A [16] is in the device
address and the Least Significant Bits A [15]-A [0] are defined in two address bytes). The most significant
word address followed by the least significant word address.
Byte Write
In the Byte Write mode, the Master device sends the Start condition and the Slave address information (with
the R/W set to Zero) to the Slave device. After the Slave generates an ACK, the Master sends the byte
REV1.0
- JUN 2014 RELEASED -
- 8 -
AITSEMI [ AiT Semiconductor ]
