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16760A 参数 Datasheet PDF下载

16760A图片预览
型号: 16760A
PDF下载: 下载PDF文件 查看货源
内容描述: 逻辑分析仪 [Logic Analyzer]
分类和应用:
文件页数/大小: 35 页 / 1054 K
品牌: AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
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Agilent 16910A and 16911A Specifications and Characteristics  
Timing (Asynchronous) Analysis Mode  
Sample rate on all channels  
Sample rate in half channel mode  
Number of channels  
Conventional Timing  
500 MHz  
Transitional Timing [8]  
500 MHz  
N/A  
1000 MHz  
16910A: 102 x (number of modules)  
16910A: For sample rates < 500 MHz:  
102 x (number of modules)  
For 500 MHz sample rate:  
102 x (number of modules) – 34  
16911A: For sample rates < 500 MHz:  
68 x (number of modules)  
16911A: 68 x (number of modules)  
For 500 MHz sample rate:  
68 x (number of modules) – 34  
Maximum channels on a single time  
base and trigger  
16910A: 510  
16911A: 340  
16910A: 510  
16911A: 340  
Number of independent analyzers [5]  
Sample period (half channel)  
Minimum sample period (full channel)  
Minimum data pulse width  
2
2
1.0 ns  
N/A  
2.0 ns  
2.0 ns  
1 sample period ꢀ 1.0 ns  
1 sample period ꢀ 1.0 ns  
Time interval accuracy  
(1 sample period ꢀ 1.25 ns ꢀ 0.01ꢁ of  
time interval reading)  
(1 sample period ꢀ 1.25 ns ꢀ 0.01ꢁ of  
time interval reading)  
Memory depth in full channel mode  
(Option 256 is included in base price)  
Option 256: 256 K samples  
Option 001: 1 M samples  
Option 004: 4 M samples  
Option 016: 16 M samples  
Option 032: 32 M samples  
Option 256: 256 K samples  
Option 001: 1 M samples  
Option 004: 4 M samples  
Option 016: 16 M samples  
Option 032: 32 M samples  
Memory depth in half channel mode  
(Option 256 is included in base price)  
Option 256: 512 K samples  
Option 001: 2 M samples  
Option 004: 8 M samples  
Option 016: 32 M samples  
Option 032: 64 M samples  
N/A  
Maximum trigger sequence speed  
Maximum trigger sequence levels  
250 MHz  
16  
250 MHz  
16  
[5] Independent analyzers may be either state or timing. When the 500 Mb/s state mode is selected, only one analyzer may be used.  
[8] Transitional timing speed and memory depth are halved unless a spare pod pair (34 channels) is unassigned.  
10