Quad Differential Receivers
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Data Sheet
April 2001
The HBM ESD threshold voltage presented here was
obtained by using the following circuit parameters:
ESD Failure Models
Agere employs two models for ESD events that can
cause device damage or failure:
Table 5. Typical ESD Thresholds for Data
Transmission Receivers
1. An HBM that is used by most of the industry for
ESD-susceptibility testing and protection-design
evaluation. ESD voltage thresholds are dependent
on the critical parameters used to define the model.
A standard HBM (resistance = 1500 Ω,
Device
HBM Threshold
CDM
Threshold
Differential Others
Inputs
BRF1A, BRR1A,
BRT1A
>800
>2000
>1000
>2000
capacitance = 100 pF) is widely used and, therefore,
can be used for comparison purposes.
BRF2A, BRS2B
>2000
>2000
2. A charged-device model (CDM), which many
believe is the better simulator of electronics
manufacturing exposure.
Table 6. ESD Damage Protection
ESD Threat Controls
Table 5 and Table 6 illustrates the role these two
models play in the overall prevention of ESD damage.
HBM ESD testing is intended to simulate an ESD event
from a charged person. The CDM ESD testing
simulates charging and discharging events that occur in
production equipment and processes, e.g., an
integrated circuit sliding down a shipping tube.
Personnel
Processes
Wrist straps.
ESD shoes.
Static-dissipative
materials.
Control
Model
Antistatic flooring.
Air ionization.
Human body
model (HBM).
Charged-device
model (CDM).
Latch Up
Latch-up evaluation has been performed on the data transmission receivers. Latch-up testing determines if power-
supply current exceeds the specified maximum due to the application of a stress to the device under test. A device
is considered susceptible to latch up if the power supply current exceeds the maximum level and remains at that
level after the stress is removed.
Agere performs latch up testing per an internal test method that is consistent with JEDEC Standard No. 17
(previously JC-40.2) CMOS Latch Up Standardized Test Procedure.
Latch up evaluation involves three separate stresses to evaluate latch up susceptibility levels:
1. dc current stressing of input and output pins.
2. Power supply slew rate.
3. Power supply overvoltage.
Table 7. Latch Up Test Criteria and Test Results
dc Current Stress
of I/O Pins
Power Supply
Slew Rate
Power Supply
Overvoltage
≥150 mA
≥250 mA
≤1 µs
≥1.75 x Vmax
≥2.25 x Vmax
Data Transmission
Receiver ICs
Minimum Criteria
Test Results
≤100 ns
Based on the results in Table 7, the data transmission receivers pass the Agere latch-up esting requirements and
are considered not susceptible to latch up.
Agere Systems Inc.
7
AGERE [ AGERE SYSTEMS ]
