Quad Differential Receivers
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Data Sheet
April 2001
Timing Characteristics
Table 4. Timing Characteristics (See Figure 4 and Figure 5.)
For propagation delays (tPLH and tPHL) over the temperature range, see Figure 9 and Figure 10.
Propagation delay test circuit connected to output is shown in Figure 6.
TA = –40 °C to +125 °C, VCC = 5 V ± 0.5 V.
Parameter
Propagation Delay:
Symbol
Min
Typ
Max
Unit
Input to Output High
tPLH
tPHL
1.5
1.5
2.5
2.5
4.0
4.0
ns
ns
Input to Output Low
Disable Time, CL = 5 pF:
High-to-high Impedance
tPHZ
tPLZ
—
—
5
5
12
12
ns
ns
Low-to-high Impedance
Pulse Width Distortion, ltpHL − tpLHI:
Load Capacitance (CL) = 15 pF
Load Capacitance (CL) = 150 pF
Output Waveform Skews:
Part-to-Part Skew, TA = 75 °C
tskew1
tskew1
—
—
—
—
0.7
4.0
ns
ns
∆tskew1p-p
—
—
—
0.8
—
1.4
1.5
0.3
ns
ns
ns
Part-to-Part Skew, TA = –40 °C to +125 °C ∆tskew1p-p
Same Part Skew
Enable Time:
∆tskew
—
High Impedance to High
High Impedance to Low
Rise Time (20%—80%)
Fall Time (80%—20%)
tPZH
tPZL
ttLH
ttHL
—
—
—
—
8
8
12
12
ns
ns
ns
ns
—
—
3.0
3.0
7
6
5
4
3
2
tPLH (TYP)
tPHL (TYP)
1
0
0
25
50
75
100 125
150
175 200
LOAD CAPACITANCE, CL (pF)
12-3462(F)
Note: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of the
delay due to the external capacitance and the intrinsic delay of the device.
Figure 3. Typical Extrinsic Propagation Delay vs. Load Capacitance at 25 °C
4
Agere Systems Inc.
AGERE [ AGERE SYSTEMS ]
