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1430G5 参数 Datasheet PDF下载

1430G5图片预览
型号: 1430G5
PDF下载: 下载PDF文件 查看货源
内容描述: NetLight 1430G5型号SONET / SDH长距离收发器,时钟恢复 [NetLight 1430G5 Type SONET/SDH Long-Reach Transceivers with Clock Recovery]
分类和应用: 时钟
文件页数/大小: 10 页 / 220 K
品牌: AGERE [ AGERE SYSTEMS ]
 浏览型号1430G5的Datasheet PDF文件第1页浏览型号1430G5的Datasheet PDF文件第3页浏览型号1430G5的Datasheet PDF文件第4页浏览型号1430G5的Datasheet PDF文件第5页浏览型号1430G5的Datasheet PDF文件第6页浏览型号1430G5的Datasheet PDF文件第7页浏览型号1430G5的Datasheet PDF文件第8页浏览型号1430G5的Datasheet PDF文件第9页  
NetLight 1430G5 Type SONET/SDH  
Long-Reach Transceivers with Clock Recovery  
Data Sheet, Rev 1.  
August 2001  
Absolute Maximum Ratings  
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-  
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess  
of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended  
periods can adversely affect device reliability.  
Parameter  
Symbol  
Min  
Max  
Unit  
Supply Voltage  
VCC  
TC  
Tstg  
0
3.6  
85  
V
°C  
Operating Case Temperature Range  
Storage Case Temperature Range  
Lead Soldering Temperature/Time  
Operating Wavelength Range  
–40  
–40  
85  
°C  
250/10  
1.6  
°C/s  
nm  
λ
1.1  
Pin Information  
TX  
RX  
20 19 18 17 16 15 14 13 12 11  
20-PIN MODULE - TOP VIEW  
1
2 3 4 5 6 7 8 9 10  
1-967(F).b  
Figure 1. 1430G5 and 1430H5-Type Transceivers, 20-Pin Configuration, Top View  
Table 1. Transceiver Pin Descriptions  
Pin  
Number  
Logic  
Family  
Symbol  
Name/Description  
Receiver  
MS  
1
MS  
Mounting Studs. The mounting studs are provided for transceiver mechani-  
cal attachment to the circuit board. They may also provide an optional con-  
nection of the transceiver to the equipment chassis ground.  
NA  
NA  
Photode- Photodetector Bias. This lead supplies bias for the PIN photodetector diode.  
tector Bias  
2
3
4
VEER  
VEER  
CLK–  
Receiver Signal Ground.  
Receiver Signal Ground.  
NA  
NA  
Received Recovered Clock Out. The rising edge occurs at the rising edge of LVPECL  
the received data output. The falling edge occurs in the middle of the received  
data bit period.  
5
CLK+  
Received Recovered Clock Out. The falling edge occurs at the rising edge  
of the received data output. The rising edge occurs in the middle of the  
received data bit period.  
LVPECL  
6
7
8
VEER  
VCCR  
SD  
Receiver Signal Ground.  
Receiver Power Supply.  
NA  
NA  
Signal Detect.  
LVTTL  
Normal operation: logic one output.  
Fault condition: logic zero output.  
9
RD–  
RD+  
Received DATA Out. No Internal terminations will be provided.  
Received DATA Out. No internal terminations will be provided.  
LVPECL  
LVPECL  
10  
2
Agere Systems Inc.