Core3DES
employ FuseLock™ technology, each of which provides a
means to keep the cipher key and the rest of the logic
secure. The output of the Core3DES macro should be
connected to registers or FIFOs, since it is only valid for
one clock cycle, as shown by example in the "Encryption"
section on page 7 and the "Decryption" section on page
8.
Design Security
Figure 5 shows a typical system diagram. Note
that the cipher key, which is the "secret" key,
can be made up of FPGA logic cells, preventing the
possibility of design or data theft. Actel Flash-based
devices (ProASICPLUS) use FlashLock™ technology, and
Actel antifuse-based devices (Axcelerator, SX-A, RTSX-S)
Actel FPGA
To other logic or
global distribution,
Local Device
Registers or
FIFO
e.g., Internet, etc.
Plaintext
(unencrypted)
Data
Encrypted
Data
Output
Other
Logic
Other
Logic
Core3DES
Source
Cipher
Key
Figure 5 • Typical Core3DES System
Core3DES Device Requirements
The Core3DES macro has been implemented in several Actel device families. Table 1 lists a summary of the
implementation data.
Table 1 • Core3DES Device Utilization and Performance
Cells or Tiles
Utilization
Device
Family
Fusion
Sequential
156
Combinatorial
Total
1413
1413
1606
772
Total
11%
11%
53%
39%
5%
Performance Throughput
1257
1257
1456
620
AFS600
75 MHz
75 MHz
50 MHz
125 MHz
81 MHz
100 MHz
60 MHz
300 Mbps
300 Mbps
66.7 Mbps
166.7 Mbps
108 Mbps
133.3 Mbps
80 Mbps
ProASIC3/E
ProASICPLUS
Axcelerator
RTAX-S
156
A3PE600-2
APA075-STD
AX125-3
150
152
152
620
772
RTAX1000S-1
A54SX16A-3
RT54SX32S-2
SX-A
152
640
792
55%
28%
RTSX-S
152
640
792
Note: Data in this table achieved using typical synthesis and layout settings
Data throughput is computed by taking the bit width of the data (64 bits), dividing by the number of cycles (48), and
multiplying by the clock rate (performance). The result is listed in Mbps (millions of bits per second).
4
v5.0
ACTEL [ Actel Corporation ]
