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3DES-SR 参数 Datasheet PDF下载

3DES-SR图片预览
型号: 3DES-SR
PDF下载: 下载PDF文件 查看货源
内容描述: [Core3DES]
分类和应用:
文件页数/大小: 13 页 / 148 K
品牌: ACTEL [ Actel Corporation ]
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Core3DES  
The Triple DES encryption algorithm is executed in the  
specific sequential order shown in Figure 2.  
2. Decrypt using DES with cipher key K2 (middle  
third of 168-bit cipher key).  
1. Encrypt using DES with cipher key K1 (left third of  
168-bit cipher key).  
3. Encrypt using DES with cipher key K3 (right third  
of 168-bit cipher key).  
K1  
K2  
K3  
DES  
(Encrypt)  
DES  
(Decrypt)  
DES  
Plaintext Data  
Ciphertext Data  
(Encrypt)  
Figure 2 Triple DES Encryption Flow Diagram  
The Triple DES decryption algorithm is executed in the  
specific sequential order shown in Figure 3.  
2. Encrypt using DES with cipher key K2 (middle third  
of 168-bit cipher key).  
1. Decrypt using DES with cipher key K3 (right third  
of 168-bit cipher key).  
3. Decrypt using DES with cipher key K1 (left third of  
168-bit cipher key).  
K3  
K2  
K1  
DES  
(Decrypt)  
DES  
(Encrypt)  
DES  
Ciphertext Data  
Plaintext Data  
(Decrypt)  
Figure 3 Triple DES Decryption Flow Diagram  
Since three sequential DES operations are required, the  
total compute time for Triple DES (encryption or  
decryption) is three times that for single DES or 16 x 3 =  
48 clock cycles.  
2. Iteration state machine logic – keeps track of  
which round of the Triple DES algorithm is  
currently in progress.  
3. Key schedule logic – computes the intermediate  
keys at each round of the Triple DES algorithm.  
Core3DES consists of four main blocks (Figure 4).  
1. Data schedule logic – computes the intermediate  
data values at each round of the Triple DES  
algorithm.  
4. Parity check logic  
checks for odd-parity  
compliance of the 168 bits of cipher key and issues  
an error signal if parity is not correct.  
Data  
schedule  
logic  
Data In  
Data Out  
Iteration  
state  
machine  
Key  
schedule  
logic  
Cipher Key  
Select Lines  
Cipher Key  
(K1,K2,K3)  
Parity  
check  
logic  
Parity Error  
Parity Enable  
Figure 4 Core3DES Block Diagram  
v5.0  
3