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3DES-UR 参数 Datasheet PDF下载

3DES-UR图片预览
型号: 3DES-UR
PDF下载: 下载PDF文件 查看货源
内容描述: [Core3DES]
分类和应用:
文件页数/大小: 13 页 / 148 K
品牌: ACTEL [ Actel Corporation ]
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Core3DES  
Encryption  
To begin the process of encrypting data, the following  
inputs are set:  
(ck3 in Figure 8) will need to be presented on the K[1:64]  
inputs, which must be done by the rising clock edge of  
the start of clock cycle 33.  
1. K[1:64] is set to the first of three cipher sub-keys  
("ck1" in Figure 8) to encrypt the data.  
After 48 clock cycles of the EN input being held  
continuously at a logic '1' value, the QVAL signal will  
transition from logic '0' to logic '1' and remain valid for  
one clock cycle, indicating that valid ciphertext  
(encrypted) data (q1 in Figure 8) is available on the  
Q[1:64] outputs. Note that the encrypted data is only  
available during clock cycle 48, thus the user must  
register or latch the data on Q[1:64], using the QVAL  
signal as a qualifying register enable or latch enable.  
2. D[1:64] is set to the plaintext data ("d1" in  
Figure 8) to be encrypted.  
3. ED is set to logic '1'.  
4. EN is set to logic '1'.  
After 15 clock cycles of the EN input being held  
continuously at a logic '1' value, the KSEL[1:0] outputs  
will change from '00' to '01', indicating that the second  
of three cipher sub-keys (ck2 in Figure 8), will need to be  
presented on the K[1:64] inputs, which must be done by  
the rising clock edge of the start of clock cycle 17 (one  
complete clock cycle of slack is built into the Core3DES  
circuitry). After 31 clock cycles of the EN input being held  
at a logic '1', the KSEL[1:0] outputs will change from '01'  
to '10', indicating that the third of three cipher sub-keys  
As shown in Figure 8, continuous encryption is possible.  
For example, the second 64-bit plaintext data word (d2  
in Figure 8) can be immediately encrypted by presenting  
d2 on the D[1:64] inputs by the rising clock edge of clock  
cycle 49 and by presenting the cipher sub-keys ck1, ck2,  
and ck3 in the sequence described earlier in this section.  
...  
...  
...  
cycle  
1
2
15 16 17 18  
31 32 33 34  
47 48 49 50  
CLK  
K[1:64]  
D[1:64]  
ED  
ck1  
d1  
ck2  
ck3  
ck1  
d2  
EN  
00  
00  
01  
01  
10  
10 00  
KSEL[1:0]  
q1  
Q[1:64]  
QVAL  
Undefined  
Don't care  
Figure 8 Example Encryption Sequence  
v5.0  
7