Core3DES
Core3DES Operation
Cipher Key Selection
Parity Checking
Since there is only one cipher key K[1:64] input port and
the Triple DES algorithm requires three 64-bit cipher sub-
keys (three 56-bit cipher sub-keys, less than 8 parity bits,
per sub-key), the three cipher sub-keys will need to be
presented in sequence on the same K[1:64] input port.
The KSEL[1:0] output port will need to be decoded by
the designer for use in external selection logic for each
of the three 64-bit cipher sub-keys. Since the KSEL[1:0]
output port may be connected to address lines of an
external RAM or ROM device, there is an extra clock cycle
of latency built into the Core3DES logic. In other words,
when the KSEL[1:0] port changes value, the next cipher
sub-key is not required immediately on the next rising
edge of the clock, however; it will be required by the
second rising edge of the clock. This is illustrated in the
"Encryption" section on page 7 and the "Decryption"
section on page 8.
If parity checking is desired for the cipher key K[1:64]
inputs, the PCHK input port should be held at logic '1.'
The parity checking logic will determine whether or not
an odd number of logic '1' values are present in each
byte of the cipher sub-keys K1, K2, and K3. This function
can be disabled at any time by setting the PCHK input to
logic '0.'
Note that if parity checking is disabled by setting the
PCHK input to logic '0', the least significant bits of each
byte of the cipher sub-keys (K[8], K[16], K[24], K[32],
K[40], K[48], K[56], and K[64]) can each be statically
connected to either a logic '1' or logic '0' value since they
are the parity bits and will not be used. Figure 7
illustrates a block diagram of the parity check logic.
K[1:64]
8
16
24
32
40
48
56
64
Parity Check
Logic
PCHK
PERR
Figure 7 • Key Parity Check
6
v5.0
ACTEL [ Actel Corporation ]
